Asus ROG STRIX Z490-E - Page 22

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ROG STRIX Z490-E BIOS Manual
The following item appears only when DRAM Command Rate is set to [N:1].
N to 1 ratio
Number of bubbles between wach valid command cycle.
Configurations: [4] - [7]
Secondary Timings
DRAM RAS# to RAS# Delay L
Configuration options: [Auto] [1] - [15]
DRAM RAS# to RAS# Delay S
Configuration options: [Auto] [1] - [15]
DRAM REF Cycle Time
Configuration options: [Auto] [1] - [1023]
DRAM REF Cycle Time 2
Configuration options: [Auto] [1] - [1023]
DRAM REF Cycle Time 4
Configuration options: [Auto] [1] - [1023]
DRAM Refresh Interval
Configuration options: [Auto] [1] - [65535]
DRAM WRITE Recovery Time
Configuration options: [Auto] [1] - [31]
DRAM READ to PRE Time
Configuration options: [Auto] [1] - [15]
DRAM FOUR ACT WIN Time
Configuration options: [Auto] [1] - [63]
DRAM WRITE to READ Delay
Configuration options: [Auto] [1] - [15]
DRAM WRITE to READ Delay L
Configuration options: [Auto] [1] - [15]
DRAM WRITE to READ Delay S
Configuration options: [Auto] [1] - [15]
DRAM CKE Minimum Pulse Width
Configuration options: [Auto] [0] - [15]
DRAM Write Latency
Configuration options: [Auto] [1] - [31]
Skew Control
ODT RTT WR (CHA)
Configuration options: [Auto] [0 DRAM CLOCK] [80 DRAM CLOCK] [120
DRAM CLOCK] [240 DRAM CLOCK] [255 DRAM CLOCK]