AT&T PC 6300 - Page 220

DIAGNOSTICS
10.
4-12
•n,
■0.
n
9. The DMA counter of the 8253 Timer is tested. The DMA
controller is disabled while the 8253 Timer is initialized. The
timer counter associated with the DMA controller has its
registers and counting ability tested in the polled mode. The
DMA controller counter is left programmed with a zero
(maximal) count to prevent the timer interfering with the "1*1
8237 DMA controller test. I I
n
The parallel printer port and the display are sent n
confirmation that the DMA counter of the 8253 Timer is M
functional. If the DMA counter test fails, a "DMA Timer
Fail" error message is sent to the display, and the CPU is
halted.
0
a
11. The 8237 DMA controller is tested. The DMA controller is
cleared and its registers, as well as the 4-bit segment latch,
are tested with fixed test patterns. The 8253 timer for the
DMA controller is programmed with the proper count in
order to refresh the dynamic RAM. All three DMA
channels are programmed with the proper mode. In order to
test the functionality of the DMA controller, the status of .
the memory refresh channel is checked for a request from j j
the timer, and the lowest bank of RAM is tested. ( i
' V
12. The parallel printer port and the display are sent i j
confirmation that the 8237 DMA Controller and the memory
refresh are functional. If the DMA Controller test fails, a
"DMA Control Fail" error message is sent to the display,
and the CPU is halted.
n
i I
n
, j
f i-
X*
0
Pi