Blu Studio 5.0 K - Page 12

[3] EA 0
[3] EA1
[3] EA 2
[3] EA3
[3] EA4
[3]
[3] EA5 EA6
[3]
[3] EA7 EA8
[3] EA9
[3] ED0
[3 ] [3 ] ED 1 E D2
ED3
[3]
[3 ] [3 ] ED 4 E D5
[3 ] [3 ] ED 6 E D7
ED8
[3]
[3] ED9
[3] ED10
[3 ] ED 11 [ 3] ED 12
[3] ED13
[3] ED14
[3] ED15
[3 ] ED 16 [ 3] ED 17
[3] ED18
[3] ED19
[3] ED20
[3 ] ED 21 [ 3] ED 22
[3] ED23
[3 ] ED 24 [ 3] ED 25
[3] ED26
[3] ED27
[3 ] ED 28 [ 3] ED 29
[3] ED30
[3] ED31
R508 240R
R507 240R
[5] NAND_D3_EMMC_VSS
Jumper for co-lay
NAND
R541--R545=0R R522=47K
[3,5] NRNB
eMMC
R529--R532=0R
[5] NAND_VCC_EMMC_VCC
[5] NAND_D15_EMMC_VCCQ
[2,3,4,5,8,9] VIO18_PMU
U501
U3 CA0 VDD1 E6
T3 CA 1 VD D1 F1
R3 CA2 VDD1 V1
R2 CA3 VDD1 W6
R1 CA4
K2 CA 5 VD D2 E5
J2 CA 6 VD D2 G2
J3 CA 7 VD D2 K1
H3 CA8 VDD2 M7
H2 CA9 VDD2 U2
T8 VDD2 W5
R8 DQ0 DQ1 VDDQ F7
R7 DQ2 VDDQ F10
R9 DQ3 VDDQ G5
R6 DQ4 Power VDDQ H9
P7 DQ5 VDDQ J10
P8 DQ6 VDDQ L6
P9 DQ7 VDDQ M6
K9 D Q8 VDDQ N6
K8 D Q9 VDDQ R10
K7 D Q10 VDDQ T9
J6 D Q11 VDDQ U5
J9 D Q12 VDDQ V7
J7 D Q13 VDDQ V10
J8 H8 DQ14 DQ15 VDDCA J1
W7 DQ16 VDDCA L1
U6 DQ17 VDDCA T2
W8 T5 DQ18 A8
U7 DQ19 DQ20 VCC VCC B2
W9 DQ21 VCCQ B8
V8 D Q22 VDDI A5
T6 H6 D Q23 DQ2 4 CLKM B5
F8 DQ25 RST C1
E9 DQ26 CMD C5
G7 DQ27 eMMC
H5 DQ28 DAT7 B4
E8 DQ29 DAT6 A4
G6 DQ30 DAT5 A6
E7 DQ31 DAT4 B6
DAT3 A7
G3 ZQ0 DAT2 B7
F3 ZQ1 DAT1 B3
DAT0 A3
F6 VSSQ CS0# P1
G10 F9 VSSQ CS1# P2
H10 VSSQ VSSQ CKE0 N1
K10 J5 VSSQ CKE1 N2
M5 VSSQ VSSQ CLK M3
P10 R5 VSSQ CLK# L3
T10 VSSQ VSSQ DQS0 P6
U10 VSSQ DQS0# P5
V6 VSSQ DQS1 K6
V9 VSSQ DQS1# K5
DQS2 U8
T1 VSSCA DQS2# U9
M1 VSSCA DQS3 G8
H1 VSSCA DQS3# G9
B9 VSSM DM0 N5
E1 VSSM DM1 L5
F2 VSS LP-DDR2 DM2 T7
F5 G1 VSS DM3 H7
L2 VSS VSS VREFCA K3
M8 U1 VSS VREFDQ M9
V2 VSS VSS NC C2
V5 VSS NC C4
C3 VSSQM NC C6
NC D1
A1 DNU NC D2
A2 DNU NC D3
A9 DNU NC D4
A10 DNU NC D5
B1 D NU NC D6
B10 DNU NC E2
E10 DNU NC E3
W1 DNU NC M2
W10 D NU NC N3
Y1 DNU NC P3
Y2 DNU NC V3
Y9 DNU NC W2
Y10 DNU NC W3
LPDDR2+eMMC (162 MCP)
R522 NC NAND
R541 NC NAND
R530 0R eMMC
C560 C550
4.7uF 220nF
R542 NC NAND
R531
[2,5] VIO_EMI R501 0R/0603
C514 C515
4.7uF 100nF
double sided SMT:
Put to the BB bottom, reserve for PI.
single sided SMT:
Put around the Memory.
VIO_EMI [2,5]
C509 C510 C511 C512 C513
100nF 100nF 100nF 100nF 4.7uF
between BB and Memory.
NAND_VCC_EMMC_VCC [5]
[5]
NAN D_D15 _EM MC _VC CQ NAND _V CC_ EMMC _V DDI [5]
NREB [3]
NLD10 [3]
NRNB [3,5] C504 C505
NALE [3] 1uF 100nF
NCLE [3]
NLD4 [3]
NLD5 [3]
NLD7 [3]
NLD14 [3]
NLD11 [3]
NWPB [5]
ECS0_B [3]
ECS1_B [3]
ECKE [3]
EDCLK [3]
EDCLK_B [3]
EDQS0 [3]
EDQS0_B [3]
EDQS1 [3]
EDQS1_B [3]
EDQS2 [3]
[3]
ED QS2_ B E DQS 3 [3]
EDQS3_B [3]
EDQM0 [3]
EDQM1 [3]
EDQM2 [3]
EDQM3 [3]
EVREF [3,5]
NLD1 [3]
NWRB [3]
NLD6 [3]
NLD8 [3]
NLD0 [3]
NLD2 [3]
NCEB [3]
NLD12 [3]
NLD13 [3]
NLD9 [3]
VIO18_PMU [2,3,4,5,8,9]
VIO18_PMU [2,3,4,5,8,9]
VEMC_3V3_PMU [4]
NLD15 [3]
VM_PMU [4]
HW trapping PIN
NC : VM=1.2V (LPDDR2)
4.7K: VM=1.8V (LPDDR1)
[3,4] PMIC_SPI_CS
[2,5] VIO_EMI
R520
8.06K/1%
[3,5] EVREF
R521
C521
100nF
8.06K/1%
0R
eMMC
VIO18_PMU [2,3,4,5,8,9]
R543
NC
NAND
[5] NAND_VCC_EMMC_VDDI
C29 C561
1uF 1uF
R545
NC NAND
WATCHDOG [3,4]
[5] NWPB R529
0R
eMMC GPIO74 [3]
[3] NLD3 R544
NC NAND
R532
0R eMMC NAND_D3_EMMC_VSS [5]