Clevo N750HU - Ps8330 B

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MINI DISPLAY PORT A(PS8330B)
DESIGN NOTE:CFG0
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
disable,no pre-emphasis, 600mVpp swing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
cancellation,3.3V IO, internal pull up at~150K
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at~150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
月
PS8330B
3.3VS
3.3VS
3.3VS
3.3VS3.3VS
3.3VS
3.3VS
3.3VS
3.3VS 3.3VS
3.3VS
3.3VS
3.3VS8,9,10,11,12,13,14,16,17,18,19,20,22,23,24,27,32,33,34,35,38
TBT_AUXN2
TBT_AUXP2
TBT_HPD18
TBT_0P2
TBT_2P2
TBT_1P2
TBT_1N2
TBT_3N2
TBT_0N2
TBT_2N2
TBT_3P2
OUT2_D0p 26
OUT2_D0n 26
OUT2_D1p 26
OUT2_D1n 26
OUT2_D2p 26
OUT2_D2n 26
OUT2_D3p 26
OUT2_D3n 26
OUT2_AUXn_SDA 26
OUT2_AUXp_SCL 26
TBT_SCL_DDC18
TBT_SDA_DDC18
OUT2_HPD 26
Title
Size Document Number Rev
Date: Sheet
of
6-71-N75H0-D01
R7.2
[25] PS8330B
A3
25 48Monday, March 20, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N75H5-001
Title
Size Document Number Rev
Date: Sheet
of
6-71-N75H0-D01
R7.2
[25] PS8330B
A3
25 48Monday, March 20, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N75H5-001
Title
Size Document Number Rev
Date: Sheet
of
6-71-N75H0-D01
R7.2
[25] PS8330B
A3
25 48Monday, March 20, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N75H5-001
C291 2.2u_6.3V_X5R_04
W/TBT
C259 0.1u_10V_X7R_04 W/TBT
C258 0.1u_10V_X7R_04 W/TBT
C260 0.1u_10V_X7R_04 W/TBT
C302 0.1u_10V_X7R_04
W/TBT
PS8330B
U12
PS8330B
W/TBT
VDD33
1
CEXT
2
I2C_ADDR
3
SCL_CTLPEQ
4
SDA_CLTCFG0
5
VDD33
6
REXT
7
CAD_SRC
8
HPD_SRC
9
CAD_SNK
10
HPD_SNK
11
VDD33
12
OUT3n
13
OUT3p
14
NC
15
OUT2n
16
OOUT2p
17
GND
18
OUT1n
19
OUT1p
20
NC
21
OUT0n
22
OUT0p
23
GND
24
VDD33
36
RST#
35
SDA_DDC
34
SCL_DDC
33
VDD33
32
GND
31
AUX_SRCp
30
AUX_SRCn
29
AUX_SNKp
28
AUX_SNKn
27
PD#
26
VDD33
25
IN3n
48
IN3p
47
NC
46
IN2n
45
IN2p
44
NC
43
IN1n
42
IN1p
41
CFG1
40
IN0n
39
IN0p
38
NC
37
EPAD
49
R171*4.7K_04
C285 2.2u_6.3V_X5R_04
W/TBT
R198
100K_04
W/TBT
C264 0.1u_10V_X7R_04 W/TBT
C261 0.1u_10V_X7R_04 W/TBT
R210 1M_04
W/TBT
R190*4.7K_04
R205
100K_04
W/TBT
C265 0.1u_10V_X7R_04 W/TBT
C309 0.1u_10V_X7R_04
W/TBT
R170*4.7K_04
R148*4.7K_04
R193*4.7K_04
C273
0.01u_16V_X7R_04
W/TBT
C262 0.1u_10V_X7R_04 W/TBT
C263 0.1u_10V_X7R_04 W/TBT
R159 10K_04
W/TBT
R197
4.99K_1%_04
W/TBT
C276
0.1u_10V_X7R_04
W/TBT
R147*4.7K_04
PS8330B_CFG0
PS8330B_CFG1
PS8330B_PEQ
PS8330B_AUXn
PS8330B_AUXp
PS8330B_CA_DET
PS8330B_CFG1
PS8330B_CFG0
TBT_HPD
PS8330B_PEQ
OUT2_D0p
OUT2_D0n
OUT2_D1n
OUT2_D1p
OUT2_D2n
TBT_SDA_DDC
TBT_SCL_DDC
PS8330B_AUXp PS8330B_AUXn
IN0P_R
IN0N_R
IN1N_R
IN1P_R
IN2N_R
IN2P_R
IN3N_R
IN3P_R
OUT2_D2p
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT2_HPD
OUT2_D3p
OUT2_D3n
Sheet 25 of 48
PS8330B
Schematic Diagrams
B - 26 PS8330B
B.Schematic Diagrams
PS8330B