R27 *10mil_short
3/23
PMSY S_PWR GD_BUF
H_PROCHOT#
H_CPUPWRGD_R
CAD N ote: Capacit or need to be pl aced
close to buff er outpu t pin
S3 circuit:- DRAM PWR GOOD logic
H_CPUPWRGD_R
R3310K_04
Processor Pullups/Pull downs
TRACE WIDTH 10MIL, LENGTH <500MILS
BUF_CPU_RST#
H_PROCHOT#
R75 *0_04
C162
47p_50V _NPO_04
R296
75_04
R74
1K_04
R294
100K_04
R293 *1K_04
R34 *10mil_short
R22 62_04
S
D
G
Q14A
MTDN 700 2ZH S6 R
2
61
S
D
G
Q14B
MTDN700 2ZHS6R
5
34
R295 43.2_1%_04
Q3
MTN70 02Z HS3
G
DS
R26 56_1%_04
R297
10K_04
C151
0.047u_10V_X7R_04
R292 130_1%_04 R62
200_1%_0 4
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U13B
T2
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK #
A27
BCLK
A28
DPLL_REF_C LK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PRO CHOT#
AL32
TH ER MTRI P#
AN32
SM_DR AMPWROK
V8
RESET#
AR33
PRDY#
AP29
PREQ#
AP27
TC K
AR26
TMS
AR27
TR ST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SY NC
AM34
SKTOCC #
AN34
PRO C_SELEC T#
C26
UNCOREPWRGOOD
AP33
Q1
MTN7002ZHS3
G
DS
R72 1K_04
C335
*68p _50V_NPO_04
R38 *51_04
R76
4.9 9K_1%_04
R105
100K_04
1.05VS
3.3VS
1.5V
1.5VS_CPU
3.3VS
1.05V S
1.05V S
CLK_EXP_N 13
CLK_EXP_P 13
CLK_DP_P 13
CLK_DP_N 13
H_PROCHOT#33
H_THRMTRIP#17
H_PECI17,2 8,29
H_PM_SYNC14,29
PLT_RST#16,22
H_CPUPWRGD17,29
DDR3_DRAMRST# 9,10
D RA MRS T_C NTR L 6 ,1 3
H_SNB_IVB#17,29
PM_DRAM_PWRGD14,2 9
XD P _ D B R _ R
SM_RC OMP_2
SM_RC OMP_1
SM_RC OMP_0H_PROCHOT# H_PROCHOT#_D
XD P _ TM S
XDP_TR ST#
XD P _ TC L K
VDDPWRGOOD_R
XDP_PR EQ#
XD P _ TD I _ R
XD P _ TD O _ R
CPUDRAMRST#
DDR3 Compensation Signals
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS .
BUF_CPU_RST#
SM_RCOMP_1
SM_RCOMP_0
XDP_BP M1 _R
XDP_BP M0 _R
SM_RCOMP_2
XDP_BP M5 _R
XDP_BP M4 _R
XDP_BP M3 _R
XDP_BP M2 _R
PMSY S_PWR GD_BUF
XDP_PR DY #
XDP_BP M7 _R
XDP_BP M6 _R
R61 *10mil _04
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
Buffered reset to CPU
S3 circuit:- DRAM_RST# to memory
should be high during S3
CPUDRAMRST#
XD P_ T D O_ R
XD P _ D B R _ R
H_CATERR#
XD P_ T R ST#
XD P_ T MS
H_SNB_IVB#
PU/PD for JTAG signals
XDP_PR EQ#
XD P_ T D I_ R
XD P_ T C LK
R60 140_1%_0 4
R57 200_1%_0 4
R53 25.5_1%_04
R36 *10mil_short
R43 *51_04
R40 *51_04
R37 *51_04
R39 51_04
R41 *51_04
CAD NOTE: All DDR_COMP signals
should be routed such that :-
- max length = 500 mils
- trace width = 15mils and
- MB trace impedance < 68 mohms
(worst case resistance)
CAD Note: Use pad sharing method
for following clock resistor placement
H_PROCHOT#_EC28
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