COMDYNA GP-6 - Page 20

OPERATOR'S
&
MAINTENANCE
MANUAL----------------------------
page
A3
911-4
QUAD
AMPLIFIER
ASSEMBLY
The
911
board
provides
two
single
input,
high
gain
operational
amplifiers
and
two
high
gain
operational
amplifiers
with
electronic
switch/integrator
networks.
Amplifiers
A
and
D
are
the
single
input
amplifiers.
Their
patch
panel
summing
junctions
are
connected
directly
to
the
interting
bases.
Back-
to-back
diodes
D2
and
D3
offer
protection
by
limiting
summing
junction
potential.
Capacitor
C1
reduces
peaking.
Amplifiers
B
and
C
are
single
input
amplifiers
with
electronic switch/integrator
networks.
The
electronic
switches
create
two
summing
junctions,
SJ
and
SJ'.
When
the
switch
control
input
(OP)
is
a logic
o
(ground
or
positive)
summing
junction
SJ'
conducts;
when
a logic 1
(more
negative
than
-5
volts)
summing
junction
SJ
conducts.
The
integrating
capacitors
are
connected
to
the
SJ
summing
junction
so
that
an
integrator
is
programmed
by
patching
an
amplifier
output to a capacitor
input.
Two
capacitor
inputs
(B
and
.1
B)
offer
10:1
time
scale
selection.
The
Time
Scale
Relay
switches
the
time
scale
change
(400:1)
that
is
required
for
high
speed
repetitive
operation.
Where
the
repetitive
operation
feature
is
provided,
the
repetitive
operation
capacitors
are
connected
directly to
SJ.
When
the
relay
is
energized,
slow
time
capacitors
are
switched
parallel
the
repetitive
operation
capacitors.
(The
relay
is
energized
when
an
approximate
negative
10
volts,
not
negative
reference,
is
applied
to
the
relay
control
input.)
Signal
switching
is
performed
by
N-channel
FET
transistors
Q6
thru
Qa.
Bipolar
transistors
Q1
thru
Q5
are
the
FET
switch
drivers.
Q6
is
the
Hold
FET
(its
an
on
resistance
is
less
than
30
ohms
to
minimize
summing
errors.)
Voltage
divider
resistors
Ra
and
R
12
are
selected
so
that
when
OP
is
between
-1
to
-3
volts,
Q6
shuts
off;
when
OP
is
more
negative
Q6
turns
on.
Q7
is
the
shunt
switch,
QB
is
the
SJ
series
switch
and
Q9
is
the
SJ'
series
switch.
Table
5-1
shows
the
switch
states
for
the
OP
logic
control
voltage
levels.
N-channel
FETs
conduct
with
a
zero
gate
voltage
and
shut
off
with
approximately-?
volts.
Back-to-back
diodes
D4
and
DS
limit
the
SJ'
potential
when
Qg
is
off.
Diodes
D2
and
D3
provide
summing
junction protection.
D1
allows
the
Hold
Inhibit
control
to
override
Q1
and
turn
Q6
on.
(Hold
Inhibit logic
is
applied
in
the
Pot
Set
Mode
to
ground
SJ
summing
junctions
that
would
otherwise
be
floating.)
Capacitors
C7
and
resistors
R
13
provide
amplifier
compensation.
Capacitorss
C1
reduces
peaking
when
SJ
has
a
resistor
feedback.
A
similar
capacitor
is
provided
the
SJ'
summing
jucntion.
BALANCING
To
balance
amplifiers
A
and
D,
patch
resistor
feedbacks
and
adjust
potentiometers
PA
and
PD
until
each
amplifier
output
is
a
zero
potential.
Amplifiers
B
and
C
should
be
balanced
when
programmed
as
integrators.
Adjust
PB
and
BC
until
each
integrator
produces
a
minimum
integrator
drift.
,.,_-----------------------------------COM
DYNA,
INC.