CONITEC GALEP-5 - Page 22

Speed
Next the number of delay cycles are given: interface_speed = 0 and jtag_speed = 100. The higher the
value, the more wait cycles are inserted between JTAG activities (one wait cycle = 1 / 60MHz). As long as no
problems with JTAG data transfer occur, no wait cycles are required.
Logic level
The logic_level = 1800 statement determines the logical high levels of the JTAG signals between 1200 and
4500 mV. !! Check the MCU data sheet for the required signal levels. Wrong values can destroy your target
system!
Socket pins
GALEP-5 allows for free assignment of JTAG signals to socket pins. Assignment start with the keywort
socket_assign and expects a signal name and a pin number. The signal names and their meaning can be
found in the following table:
a
Can be assigned to several pins.
b
Value depends on vcc_level VCCx = mV.
c
Parameter (range) depends on logic_level = mV.
The JTAG relevant signals must be only specified once. GND and VCC however can be specified several
times for different pins. The following image displayes the socket pins of the example:
Signal name Meaning Direction Parameter Remark
TargetDetect See below Target ► GALEP-5 1.2 - 25V
VCC1 See below GALEP-5 ► Target 1.2 - 25V
a b
VCC2 See below GALEP-5 ► Target 1.2 - 25V
a b
VCC3 See below GALEP-5 ► Target 1.2 - 25V
a b
GND See below GALEP-5 ► Target 0V
a
NRESET3v3 Target Reset Signal GALEP-5 ► Target 3.3V
NRESET Target Reset Signal GALEP-5 ► Target 1.2V - 4.5V
c
NTRST JTAG Reset GALEP-5 ► Target 1.2V - 4.5V
c
TDI GALEP-5 ► Target 1.2V - 4.5V
c
TMS GALEP-5 ► Target 1.2V - 4.5V
c
TCK GALEP-5 ► Target 1.2V - 4.5V
c
TDO Target ► GALEP-5 1.2V - 4.5V
c