DATA PRECISION 5740 - Period Measurement Block Diagram; Stopwatch Operation Block Diagram

72-1002
Model 5740 COUNTER
In operation, input signals of sine
waves or pulse trains are converted to a
TTL compatible pulse train by the input
signal conditioning circuitry and gated to
the counter by control signals from the
intercycle control circuitry. The Pro
grammable Divider operates on the gated
IMHz time base and counts down according
to the selected GATE TIME.
At the end of the selected GATE TIME
interval, the Intercycle Control Circuit
ry removes the enabling level from the
Counter Gate, thereby stopping the count
er. At the same time, a three-step
counter in the Intercycle Control gener
ates control signals to:
1) Transfer the value from the Count
er to a Latching Register which automat
ically updates the Display,
2) Reset the Counter in preparation
for the next conversion cycle and,
3) Initiate the next conversion cycle
by enabling the counter gate.
The sequence of control actions is ac
complished in approximately 0.3 sec.
3.2.2 Measuring PERIOD
As shown in Figure 3-2,
switch S4 is moved to the
tion, the input signal is
Programmable Divider and
base pulse train is gated
er-Latch-Display. Rotary
used to select the number
input signal counted down
when slide
PERIOD posi-
gated to the
the IMHz time
to the Count-
switch S3 is
of periods of
before trans
mitting a control indicator to the
Intercycle Control circuitry. The
Counter Gate is enabled for a selected
number of input signal transitions
(Periods) under control of the Inter
cycle Control circuit. As before, the
Intercycle Control circuitry steps the
value from the Counter to the Latch and
thence to the Display, and sequences the
circuit through RESET and the start of
the next measurement cycle. The inter
val between such measurements is simi
larly approximately 0.3 sec.
3.2.3 Counting Time Increments (SECONDS)
As shown in Figure 3-3, when slide
switch 84 is placed in SECONDS opera
tion, the IMHz time base signal is gated
into the Programmable Divider which, in
turn, is programmed to divide by 10,000,
so that a timing signal pulse train of
0.01 seconds interval is developed at
its output and connected to the Counter
Gate. The Counter Gate is controlled by
the action of rotary switch S3 which by
passes the Intercycle Counter program
ming control. At all times the Counter
output is transferred to the Latching
register and continuously updates the
Display.
The Divider-to-Counter Gate is enabled
whenever Switch S3 is in the SEC/EVENTS
position, permitting the time increments
to accumulate. When S3 is placed in the
HOLD position, the enable level is removed
from the Counter Gate, and the count value
remains. Returning S3 to the SEC/EVENTS
position restores the enable level to the
Counter Gate and the value in the counter
H
INPUT
MODE
SIGNAL
GATE
CONDIT
10
1
MHZ
MHZ
MODE
GATE
COUNT
GATE
PERIODS AVGD
» ^ 1 RESET
71 .
PROGRAM.
INTERCYCLE
DIVIDER
CONTROL
SYNCH START MEASURF
Fig. 3-2. Model 5740 PERIOD Measurement Simplified Block Diagram
3-2
COPYRIGHT 1975 DATA PRECISION CORPORATION PRINTED IN THE US.A.