Feature Description
generations of this technology, from software to clocking
architecture to mechanical interfaces.
AHCI The SATA controller provides hardware support for Advanced
Host Controller Interface (AHCI), a standardized programming
interface for SATA host controllers developed through a joint
industry eort. Platforms supporting AHCI may take advantage
of performance features such as port independent DMA Engines
—each device is treated as a master—and hardware-assisted
native command queuing.
AHCI denes transactions between the SATA controller and
software and enables advanced performance and usability with
SATA. Platforms supporting AHCI may take advantage of
performance features such as no master/slave designation for
SATA devices—each device is treated as a master— and
hardware assisted native command queuing. AHCI also provides
usability enhancements such as hot-plug and advanced power
management. AHCI requires appropriate software support (such
as, an AHCI driver) and for some features, hardware support in
the SATA device or additional platform hardware. Visit the Intel
web site for current information on the AHCI specication.
Low Pin Count Interface (LPC) The Low Pin Count (LPC) Interface Specication for legacy I/O
has facilitated the industry's transition toward ISA-less systems.
The key enhancements to the 1.1 revision of the LPC Interface
Specication is the inclusion of Firmware Memory cycles and
addition of multibyte read capability.
The LPC Interface allows the legacy I/O motherboard
components, typically integrated in a Super I/O chip, to migrate
from the ISA/X-bus to the LPC Interface, while retaining full
software compatibility. The LPC Specication oers several key
advantages over ISA/X-bus, such as reduced pin count for
easier, more cost-eective design. The LPC Interface
Specication is software transparent for I/O functions and
compatible with existing peripheral devices and applications.
The LPC Interface Specication describes memory, I/O and
DMA transactions. Unlike ISA, which runs at 8MHz, it will use
the PCI 33MHz clock and will be compatible with more
advanced silicon processes. Mobile designers will also benet
from the reduced pin count because it uses less space and
power and is more thermal ecient.
Serial Peripheral Interface (SPI) The interface implements 3 Chip Select signals (CS#), allowing
up to two ash devices and one TPM device to be connected to
the PCH. The CS0# and CS1# are used for ash devices and
CS2# is dedicated to TPM.
Advanced Programmable Interrupt Controller (APIC) The chipset contains a Motorola MC146818B-compatible real-
time clock with 256 bytes of battery-backed RAM. The Real-
Time Clock (RTC) performs two key functions—keeping track
of the time of day and storing system data, even when the
system is powered down. The RTC operates on a 32.768-KHz
crystal and a 3V battery.
GPIO GPIO Serial Expander (GSX) is the capability provided by the
chipset to expand the GPIOs on a platform that needs more
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