Supported Processors
Processor Clock Speed Cache QPI Cores/Threads Turbo TDP
E5-2699 v4 2.2 GHz 55M 9.6 GT/s 22/44 Turbo 145 W
E5-2698 v4 2.2 GHz 50M 9.6 GT/s 20/40 Turbo 135 W
E5-2697A v4 2.6 GHz 40M 9.6 GT/s 16/32 Turbo 145 W
E5-2697 v4 2.3 GHz 45M 9.6 GT/s 18/36 Turbo 145 W
E5-2695 v4 2.1 GHz 45M 9.6 GT/s 18/36 Turbo 120 W
E5-2690 v4 2.6 GHz 35M 9.6 GT/s 14/28 Turbo 135 W
E5-2687 v4 3.0 GHz 30M 9.6 GT/s 12/24 Turbo 160 W
E5-2683 v4 2.1 GHz 40M 9.6 GT/s 16/32 Turbo 120 W
E5-2680 v4 2.4 GHz 35M 9.6 GT/s 14/28 Turbo 120 W
E5-2667 v4 3.2 GHz 25M 9.6 GT/s 8/16 Turbo 135 W
E5-2660 v4 2.0 GHz 35M 9.6 GT/s 14/28 Turbo 105 W
E5-2650L v4 1.7 GHz 35M 9.6 GT/s 14/28 Turbo 65 W
E5-2650 v4 2.2 GHz 30M 9.6 GT/s 12/24 Turbo 105 W
E5-2643 v4 3.4 GHz 20M 9.6 GT/s 6/12 Turbo 135 W
E5-2640 v4 2.4 GHz 25M 8.0 GT/s 10/20 Turbo 90 W
E5-2637 v4 3.5 GHz 15M 9.6 GT/s 4/8 Turbo 135 W
E5-2630L v4 1.8 GHz 25M 8.0 GT/s 10/20 Turbo 55 W
E5-2630 v4 2.2 GHz 20M 8.0 GT/s 8/16 Turbo 85 W
E5-2623 v4 2.6 GHz 10M 9.6 GT/s 4/8 Turbo 85 W
E5-2620 v4 2.1 GHz 20M 8.0 GT/s 8/16 Turbo 85 W
E5-2609 v4 1.7 GHz 20M 6.40 GT/s 8/8 No Turbo 85 W
E5-2603 v4 1.7 GHz 15M 6.40 GT/s 6/6 No Turbo 85 W
Chipset
The Intel C610 chipset is implemented on the PowerEdge R730 and R730xd.
The QuickPath Architecture consists of serial point-to-point interconnects for the processors. The PowerEdge R730 and
R730xd have a total of two QuickPath Interconnect (QPI) links connecting the processors.
● Each link consists of 20 lanes (full-width) in each direction with a link speed of 9.6 GT/s.
● An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as packets.
● The QuickPath Architecture implemented in E5-2600 v3 features four layers.
● The Physical layer consists of the actual connection between components. It supports Polarity Inversion and Lane Reversal
for optimizing component placement and routing.
● The Link layer is responsible for flow control and the reliable transmission of data. The Link layer also provides independent
flow control for each message class going to and from the Routing Layer.
● The Routing layer is implemented in a distributed manner between all agents that send Intel QPI messages on the ring (Intel
QPI Module, Cbo, IIO, HA). The Intel QPI Module provides a routing function for determining the correct ring stop to forward
an inbound packet.
● The Protocol layer is responsible for high-level protocol communications, including the implementation of a MESIF (Modify,
Exclusive, Shared, Invalid, and Forward) cache coherence protocol.
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Technology and Components
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