Dell PowerEdge XR5610 - Page 53

Table 49. Processor Settings details(continued)
Option Description
entered decreases the Dell AVX Scaling Technology frequency when the
Dell-controlled Turbo feature is enabled.
Number of Cores per Processor Controls the number of enabled cores in each processor. This option is
set to All by default.
CPU Physical Address Limit Limit CPU physical address to 46 bits to support older Hyper-V. If
enabled, automatically disables TME-MT. This option is set to Enabled
by default.
AMP Prefetch This option enables one of the Mid-Level Cache (MLC) AMP hardware
Prefetcher. This option is set to Disabled by default.
Homeless Prefetch This option allows L1 Data Cache Unit (DCU) to prefetech, when the Fill
Buffers (FB) is full. Auto maps to hardware default setting. This option
is set to Auto by default.
Unicore Frequency RAPL This setting controls whether the Running Average Power Limit (RAPL)
balancer is enabled or not. If enabled, it activates the uncore power
budgeting. This option is set to Enabled by default.
Processor Core Speed Specifies the maximum core frequency of the processor.
Local Machine Check Exception Enables or disables the local machine check exception. This is an
extension of the MCA Recovery mechanism providing the capability to
deliver Uncorrected Recoverable (UCR) Software Recoverable Action
Required (SRAR) errors to one or more specific logical processors
threads receiving previously poisoned or corrupted data. When enabled,
the UCR SRAR Machine Check Exception is delivered only to the
affected thread rather than broadcast to all threads in the system.
The feature supports operating system recovery for cases of multiple
recoverable faults that are detected close, which would otherwise
result in a fatal machine check event. The feature is available only on
Advanced RAS processors. This option is set to Enabled by default.
CPU Crash Log Support This field controls Intel CPU Crash Log feature for collection of previous
crash data from shared SRAM of Out-of -Band Management Service
Module at post reset. This option is set to Disabled by default.
PROCESSOR 1
NOTE: Depending on the number of processors, there might be up
to n processors listed.
The following settings are displayed for each processor:
Table 50. Processor n details
Option Description
Family-Model-Stepping Specifies the family, model, and stepping of the processor as
defined by Intel.
Brand Specifies the brand name.
Level 2 Cache Displays the amount of memory in the processor cache
Level 3 Cache Displays the amount of memory in the processor cache
Number of Cores Specifies the number of cores per processor.
Maximum Memory Capacity Specifies the maximum memory capacity per processor.
Microcode Specifies the processor microcode version.
Pre-operating system management applications 53