27
D-107
1 REV
5CH output change terminal, logic input of
loading block
2 S-Vcc
signal system power supply
(BTL-AMP:CH1~4)
3 Vcc2 Power supply for loading block
4 VL0− Loading output (−)
5 VL0+ Loading output (+)
6 VO4+ Output terminal (+) for channel 4
7 VO4− Output terminal (−) for channel 4
8 VO3+ Output terminal (+) for channel 3
9 VO3− Output terminal (−) for channel 3
10 VO2+ Output terminal (+) for channel 2
11 VO2− Output terminal (−) for channel 2
12 VO1+ Output terminal (+) for channel 1
13 VO1− Output terminal (−) for channel 1
14 Vcc1 CH1 CH4(BTL-AMP) output stage power supply
15 VIN1 Input terminal for channel 1
16 VIN1− OP-AMP input AMP-A input terminal (−)
17 VIN1+ OP-AMP input AMP-A input terminal (+)
18 VIN2 Input terminal for channel 2, input AMP output
19 VIN2− Input terminal (−) for channel 2
20 VIN2+ Input terminal (+) for channel 2
21 Vcc-VREG 3.3VREG power supply
22 GND-VREG 3.3VREG GND
23 VIN3 Input terminal for channel 3, input AMP output
24 VIN3− Input terminal (−) for channel 3
25 VIN3+ Input terminal (+) for channel 3
26 REG-IN PNP transistor base connected
27 REG-OUT
3.3V power output to which the PNP transistor
collector connected
28 VCONT Loading output voltage set terminal
29 VREF-IN Reference voltage applied terminal
30 VIN4+ Input terminal (+) for channel 4
31 VIN4- Input terminal (−) for channel 4
32 VIN4 Input terminal for channel 4, input AMP output
33 MUTE1 Output ON/OFF for channel 1 (BTL AMP)
34 MUTE2 Output ON/OFF for channel 2 to 4 (BTL AMP)
35 S-GND Signal system GND
36 FWD
Output change terminal (FWD) for loading
output (VLO+−), logic input of loading block
Pin
No.
Name
Function
1
2
3
4
5
6
7
8
9
FR
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
FR
27
26
25
24
23
22
21
20
19
FWD
S-GND
MUTE2
MUTE1
VIN4
VIN4-
VIN4+
VREF-IN
VCONT(LOADING
FR
REG-OUT
REG-IN
VIN3+
VIN3-
VIN3
GND-VREG
VCC-VREG
VIN2+
VIN2-
REV
S-VCC
VCC2
VLO-
VLO+
VO4+
VO4-
VO3+
VO3-
FR
VO2+
VO2-
VO1+
VO1-
VCC1
VIN1
VIN1-
VIN1+
VIN2
Signal System VCC
(CH1 to CH4)
33k
11k
33k
11k
3.3VREG GND
3.3VREG
33k
11k
3.3VREG
PNP Tr
Base
PNP Tr
Collector
33k
11k
CH1 Output
ON/OFF
CH2 to CH4
Output
MUTE1
MUTE2
(LOADING)
Power Supply
Input
(Forward/Reverse/
Break/OFF)
Output
Control
Level
Shift
Level
Shift
Power
System
GND
Level
Shift
Level
Shift
Power Supply
Power Supply
(External PNP)
Power System GND
Signal System GND
Thermal
Shutdown
LA6559 (IC201)
Clock Generator No.1
Mode Control
Clock Generator No.2
Clock Generator No.3
Lower Byte Upper Byte
I/O1
I/O8 I/O9 I/O16
Data Input Buffer
Data Output Buffer
RAS Vcc
Vss
WE
I/O1
I/O16
OE
A0
A8
UCAS
LCAS
Refresh Counter
Row Address
Buffer
Column Address
Buffer
Column Decoder
Pre-Decoder
PWB Bias Generator
Sense Amp
I/O Gate
262144 Memory Cell
x16 Bit
512x16
512
512
I/O1
I/O8 I/O9 I/O16
Row Decoder
LC32V4265T-25
(IC208)
1
2
3
4
5
6
7
8
9
10
36
35
34
33
31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20
V
CC
I/O1
I/O2
I/O3
I/O4
V
CC
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
RAS
N.C.
A0
A1
A2
A3
V
CC
VSS
I/O16
I/O15
I/O14
I/O13
V
SS
I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS21
32
40
39
38
37
TOP VIEW
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Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
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