36
DN-HS5500
66 PE13 AMUTE O - Analog MUTE
67 -CS0 CS0 O - External memory chip select 0
68 -CS1 CS1 O - External memory chip select 1
69 SCK2 CFGCLK O - Serial clock output (FPGA CFG CLK)
70 DREQ3 DREQ3 - Not used
71 PINT7 PINT7 I - LCD synchronized read trigger
72 SDA HIICDAT I/O - IIC serial data input/output
73 SCL HIICCLK I/O - IIC serial data clock input/output
74 -BS SHBS O - Bus-cycle start signal
75 DREQ0 DREQ0 I - Direct memory access transfer request 0
76 PVcc V3SH I - - - - I/O supply (+3.3V)
77PVss D_GND -----GND
78 Vss D_GND - - - - - GND
79 Vcc V1SH I - - - - Core supply (+1.2V)
80 PE3 PE3 O - FPGA configuration status signal
81 TxD0 TxD0 O - D-Sync output
82 -CS6 CS6 O - External chip select 6
83 PE1 CONFIG O -
Configuration L → H configuration start
84 -CS7 CS7 O - External chip select 7
85 RxD0 RxD0 I - D-Sync input
86 PE4 PE4 I/O - Configuration done
87 DREQ1 DREQ1 I - Direct memory access transfer request 1
88 DACK0 DACK0 O - Direct memory access request answer 0
89AVss D_GND -----GND
90 AN0 AN0 I - Slid VR PANEL 1 data input for pitch
91 AN1 D_GND I - Not used
92 AN2 D_GND - - - - - GND
93 AN3 D_GND - - - - - GND
94 AN4 D_GND - - - - - GND
95 AN5 D_GND - - - - - GND
96 AN6 LCDVCON O - LCD cont.
97 AN7 MPSD O - DD motor engine speed control
98 Avref +3.3V I - Analog reference voltage for A/D converter
99 Avcc +3.3V I - Analog power supply for A/D converter
100 TxD2 CFGDAT O - Configuration data
101 Vcc V1SH I - - - - Core supply (+1.2V)
102Vss D_GND -----GND
103 RxD3 RxD3 I - Not used
104 -ASEBRKAK -ASEBRKAK O - Break acknowledge for emulator (for debug)
105 TxD3 - - Not used
106 -WDTOVF - - Not used
107 ASEBCK - - Not used
108 PVcc V3SH I - - - - I/O supply (+3.3V)
109 PINT3 PINT3 - PS2 data communication interrupt
110 TCK TCK I - Test clock input (for debug)
111 -TRST -TRSET I - Test reset input (for debug)
112 TDI TDI I - Test data input (for debug)
113PVss D_GND -----GND
114Vss D_GND -----GND
115 Vcc V1SH I - - - - Core supply (+1.2V)
116 TMS TMS I - Test mode select input (for debug)
117 PVcc V3SH I - - - - I/O supply (+3.3V)
118PVss D_GND -----GND
119 -ASEMD -ASEMD I - Debug mode enable input (for debug)
120 TDO TDO O - Test data output (for debug)
121 D31 ..SHDB31 I/O - - - - Data bus 31
122 D30 ..SHDB30 I/O - - - - Data bus 30
123 D29 ..SHDB29 I/O - - - - Data bus 29
124 D28 ..SHDB28 I/O - - - - Data bus 28
125 PVcc V3SH I - - - - I/O supply (+3.3V)
126PVss D_GND -----GND
127 D27 ..SHDB27 I/O - - - - Data bus 27
128 D26 ..SHDB26 I/O - - - - Data bus 26
129 D25 ..SHDB25 I/O - - - - Data bus 25
130 D24 ..SHDB24 I/O - - - - Data bus 24
131 PVcc V3SH I - - - - I/O supply (+3.3V)
132 D23 ..SHDB23 I/O - - - - Data bus 23
Pin No. Pin Name Symbol I/O DET Ext Ini Res Function
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