Functional Description
3.4 Active Burst Mode Operation
At very low load condition, the IC enters active burst
mode operation to minimize the input power. Details
about active burst mode operation are explained in the
following paragraphs.
3.4.1 Entering Active Burst Mode Operation
For determination of entering active burst mode
operation, three conditions apply:
the regulation voltage is lower than the threshold of
V
EB
(1.1V). Accordingly, the peak voltage across the
shunt resistor is 0.11V;
the up/down counter has its maximal value of 7; and
a certain blanking time (24ms).
Once all of these conditions are fulfilled, the active
burst mode flip-flop is set and the controller enters
burst mode operation. This multi-conditional
determination for entering active burst mode operation
prevents mistriggering of entering active burst mode
operation, so that the controller enters active burst
mode operation only when the output power is really
low during the preset blanking time.
3.4.2 During Active Burst Mode Operation
After entering the Active Burst Mode the regulation
voltage rises as V
OUT
starts to decrease due to the
inactive PWM section. One comparator observes the
regulation signal if the voltage level V
BH
(3.6V) is
exceeded. In that case the internal circuit is again
activated by the internal bias to start with swtiching.
Turn-on of the power MOSFET is triggered by the
timer. The PWM generator for burst mode operation
composes of a timer with a fixed frequency of 80kHz,
typically, and an analog comparator. Turn-off is
resulted by comparison of the voltage signal v
1
with an
internal threshold, by which the voltage across the
shunt resistor V
csB
is 0.25V, accordingly. A turn-off can
also be triggered by the maximal duty ratio controller
which sets the maximal duty ratio to 50%. In operation,
the output flip-flop will be reset by one of these signals
which come first.
If the output load is still low, the regulation signal
decreases as the PWM section is operating. When
regulation signal reaches the low threshold V
BL
(3.0V),
the internal bias is reset again and the PWM section is
disabled until next time regultaion siganl increases
beyond the V
BH
threshold. If working in active burst
mode the regulation signal is changing like a saw tooth
between 3.0V and 3.6V shown in Figure 6.
3.4.3 Leaving Active Burst Mode
The regulation voltage immediately increases if there is
a high load jump. This is observed by one comparator.
As the current limit is 25% during active burst mode a
certain load is needed so that regulation voltage can
exceed V
LB
(4.5V). After leaving active busrt mode,
maximum current can now be provided to stabilize V
O
.
In addition, the up/down counter will be set to 1
immediately after leaving active burst mode. This is
helpful to decrease the output voltage undershoot.
3.4.4 IC Power Supply During Active Burst
Mode
During active burst mode operation, the power cell is
activated again. Once the power from the auxiliary
winding is not high enough to keep the VCC voltage
above the preset value of V
VCCBL
, the power cell keeps
the VCC voltage at the preset value V
VCCBL
. Otherwise,
if the VCC voltage is still above this value, no current
flows through the power cell though it is activated.
Figure 6 Signals in active burst mode
1.1V
3.6V
4.4V
V
REG
t
0.25V
1.0V
V
CS
12.5V
V
VCC
t
t
V
O
t
3.0V
Max. Ripple < 1%
Blanking Window (24ms)
Current limit level
during Active Burst
Mode
Leaving
Active Burst
Mode
Entering
Active Burst
Mode
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