Eaton EDR 3000 - Page 738

EDR-3000 IM02602003E
Name Description
Logic.LE4.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE4.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE5.Gate Out Signal: Output of the logic gate
Logic.LE5.Timer Out Signal: Timer Output
Logic.LE5.Out Signal: Latched Output (Q)
Logic.LE5.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE5.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE5.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE6.Gate Out Signal: Output of the logic gate
Logic.LE6.Timer Out Signal: Timer Output
Logic.LE6.Out Signal: Latched Output (Q)
Logic.LE6.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE6.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE6.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE7.Gate Out Signal: Output of the logic gate
Logic.LE7.Timer Out Signal: Timer Output
Logic.LE7.Out Signal: Latched Output (Q)
Logic.LE7.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE7.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE7.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE8.Gate Out Signal: Output of the logic gate
Logic.LE8.Timer Out Signal: Timer Output
Logic.LE8.Out Signal: Latched Output (Q)
Logic.LE8.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE8.Gate In1-I State of the module input: Assignment of the Input Signal
www.eaton.com 726