Eaton EDR 3000 - Page 740

EDR-3000 IM02602003E
Name Description
Logic.LE12.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE12.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE13.Gate Out Signal: Output of the logic gate
Logic.LE13.Timer Out Signal: Timer Output
Logic.LE13.Out Signal: Latched Output (Q)
Logic.LE13.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE13.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE13.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE13.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE13.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE13.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE14.Gate Out Signal: Output of the logic gate
Logic.LE14.Timer Out Signal: Timer Output
Logic.LE14.Out Signal: Latched Output (Q)
Logic.LE14.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE14.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE14.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE14.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE14.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE14.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE15.Gate Out Signal: Output of the logic gate
Logic.LE15.Timer Out Signal: Timer Output
Logic.LE15.Out Signal: Latched Output (Q)
Logic.LE15.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE15.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE15.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE15.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE15.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE15.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE16.Gate Out Signal: Output of the logic gate
Logic.LE16.Timer Out Signal: Timer Output
Logic.LE16.Out Signal: Latched Output (Q)
Logic.LE16.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE16.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE16.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE16.Gate In3-I State of the module input: Assignment of the Input Signal
www.eaton.com 728