Eaton EDR 3000 - Page 743

EDR-3000 IM02602003E
Name Description
Logic.LE25.Gate Out Signal: Output of the logic gate
Logic.LE25.Timer Out Signal: Timer Output
Logic.LE25.Out Signal: Latched Output (Q)
Logic.LE25.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE25.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE25.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE25.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE25.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE25.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE26.Gate Out Signal: Output of the logic gate
Logic.LE26.Timer Out Signal: Timer Output
Logic.LE26.Out Signal: Latched Output (Q)
Logic.LE26.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE26.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE26.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE26.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE26.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE26.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE27.Gate Out Signal: Output of the logic gate
Logic.LE27.Timer Out Signal: Timer Output
Logic.LE27.Out Signal: Latched Output (Q)
Logic.LE27.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE27.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE27.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE27.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE27.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE27.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE28.Gate Out Signal: Output of the logic gate
Logic.LE28.Timer Out Signal: Timer Output
Logic.LE28.Out Signal: Latched Output (Q)
Logic.LE28.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE28.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE28.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE28.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE28.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE28.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE29.Gate Out Signal: Output of the logic gate
www.eaton.com 731