Eaton EDR-5000 - Page 984

EDR-5000 IM02602007E
Name Description
Logic.LE6.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE7.Gate Out Signal: Output of the logic gate
Logic.LE7.Timer Out Signal: Timer Output
Logic.LE7.Out Signal: Latched Output (Q)
Logic.LE7.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE7.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE7.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE7.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE8.Gate Out Signal: Output of the logic gate
Logic.LE8.Timer Out Signal: Timer Output
Logic.LE8.Out Signal: Latched Output (Q)
Logic.LE8.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE8.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE8.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE8.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE8.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE8.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE9.Gate Out Signal: Output of the logic gate
Logic.LE9.Timer Out Signal: Timer Output
Logic.LE9.Out Signal: Latched Output (Q)
Logic.LE9.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE9.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE9.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE9.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE10.Gate Out Signal: Output of the logic gate
Logic.LE10.Timer Out Signal: Timer Output
Logic.LE10.Out Signal: Latched Output (Q)
Logic.LE10.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE10.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE10.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE10.Reset Latch-I State of the module input: Reset Signal for the Latching
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