Eaton EDR-5000 - Page 985

EDR-5000 IM02602007E
Name Description
Logic.LE11.Gate Out Signal: Output of the logic gate
Logic.LE11.Timer Out Signal: Timer Output
Logic.LE11.Out Signal: Latched Output (Q)
Logic.LE11.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE11.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE11.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE11.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE12.Gate Out Signal: Output of the logic gate
Logic.LE12.Timer Out Signal: Timer Output
Logic.LE12.Out Signal: Latched Output (Q)
Logic.LE12.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE12.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE12.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE12.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE13.Gate Out Signal: Output of the logic gate
Logic.LE13.Timer Out Signal: Timer Output
Logic.LE13.Out Signal: Latched Output (Q)
Logic.LE13.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE13.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE13.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE13.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE13.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE13.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE14.Gate Out Signal: Output of the logic gate
Logic.LE14.Timer Out Signal: Timer Output
Logic.LE14.Out Signal: Latched Output (Q)
Logic.LE14.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE14.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE14.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE14.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE14.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE14.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE15.Gate Out Signal: Output of the logic gate
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