Eaton EDR-5000 - Page 987

EDR-5000 IM02602007E
Name Description
Logic.LE19.Out Signal: Latched Output (Q)
Logic.LE19.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE19.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE19.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE19.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE19.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE19.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE20.Gate Out Signal: Output of the logic gate
Logic.LE20.Timer Out Signal: Timer Output
Logic.LE20.Out Signal: Latched Output (Q)
Logic.LE20.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE20.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE20.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE20.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE20.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE20.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE21.Gate Out Signal: Output of the logic gate
Logic.LE21.Timer Out Signal: Timer Output
Logic.LE21.Out Signal: Latched Output (Q)
Logic.LE21.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE21.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE21.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE21.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE21.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE21.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE22.Gate Out Signal: Output of the logic gate
Logic.LE22.Timer Out Signal: Timer Output
Logic.LE22.Out Signal: Latched Output (Q)
Logic.LE22.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE22.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE22.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE22.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE22.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE22.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE23.Gate Out Signal: Output of the logic gate
Logic.LE23.Timer Out Signal: Timer Output
Logic.LE23.Out Signal: Latched Output (Q)
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