Eaton EDR-5000 - Page 988

EDR-5000 IM02602007E
Name Description
Logic.LE23.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE23.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE23.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE23.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE23.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE23.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE24.Gate Out Signal: Output of the logic gate
Logic.LE24.Timer Out Signal: Timer Output
Logic.LE24.Out Signal: Latched Output (Q)
Logic.LE24.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE24.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE24.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE24.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE24.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE24.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE25.Gate Out Signal: Output of the logic gate
Logic.LE25.Timer Out Signal: Timer Output
Logic.LE25.Out Signal: Latched Output (Q)
Logic.LE25.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE25.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE25.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE25.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE25.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE25.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE26.Gate Out Signal: Output of the logic gate
Logic.LE26.Timer Out Signal: Timer Output
Logic.LE26.Out Signal: Latched Output (Q)
Logic.LE26.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE26.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE26.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE26.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE26.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE26.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE27.Gate Out Signal: Output of the logic gate
Logic.LE27.Timer Out Signal: Timer Output
Logic.LE27.Out Signal: Latched Output (Q)
Logic.LE27.Out inverted Signal: Negated Latched Output (Q NOT)
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