Eaton EDR-5000 - Page 989

EDR-5000 IM02602007E
Name Description
Logic.LE27.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE27.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE27.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE27.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE27.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE28.Gate Out Signal: Output of the logic gate
Logic.LE28.Timer Out Signal: Timer Output
Logic.LE28.Out Signal: Latched Output (Q)
Logic.LE28.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE28.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE28.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE28.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE28.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE28.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE29.Gate Out Signal: Output of the logic gate
Logic.LE29.Timer Out Signal: Timer Output
Logic.LE29.Out Signal: Latched Output (Q)
Logic.LE29.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE29.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE29.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE29.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE29.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE29.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE30.Gate Out Signal: Output of the logic gate
Logic.LE30.Timer Out Signal: Timer Output
Logic.LE30.Out Signal: Latched Output (Q)
Logic.LE30.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE30.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE30.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE30.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE30.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE30.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE31.Gate Out Signal: Output of the logic gate
Logic.LE31.Timer Out Signal: Timer Output
Logic.LE31.Out Signal: Latched Output (Q)
Logic.LE31.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE31.Gate In1-I State of the module input: Assignment of the Input Signal
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