Eaton EDR-5000 - Page 1008

EDR-5000 IM02602007E
Name Description
Statistics.StartFc P Demand-I State of the module input: Start of Statistics of the Active Power Demand
Logic.LE1.Gate Out Signal: Output of the logic gate
Logic.LE1.Timer Out Signal: Timer Output
Logic.LE1.Out Signal: Latched Output (Q)
Logic.LE1.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE1.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE1.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE2.Gate Out Signal: Output of the logic gate
Logic.LE2.Timer Out Signal: Timer Output
Logic.LE2.Out Signal: Latched Output (Q)
Logic.LE2.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE2.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE2.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE3.Gate Out Signal: Output of the logic gate
Logic.LE3.Timer Out Signal: Timer Output
Logic.LE3.Out Signal: Latched Output (Q)
Logic.LE3.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE3.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE4.Gate Out Signal: Output of the logic gate
Logic.LE4.Timer Out Signal: Timer Output
Logic.LE4.Out Signal: Latched Output (Q)
Logic.LE4.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE4.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE4.Reset Latch-I State of the module input: Reset Signal for the Latching
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