Eaton EMR-4000 - Page 823

EMR-4000 IM02602009E
Name Description
IEC61850.VirtInp25 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp26 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp27 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp28 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp29 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp30 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp31 Signal: Virtual Input (IEC61850 GGIO Ind)
IEC61850.VirtInp32 Signal: Virtual Input (IEC61850 GGIO Ind)
Logic.LE1.Gate Out Signal: Output of the logic gate
Logic.LE1.Timer Out Signal: Timer Output
Logic.LE1.Out Signal: Latched Output (Q)
Logic.LE1.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE2.Gate Out Signal: Output of the logic gate
Logic.LE2.Timer Out Signal: Timer Output
Logic.LE2.Out Signal: Latched Output (Q)
Logic.LE2.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate Out Signal: Output of the logic gate
Logic.LE3.Timer Out Signal: Timer Output
Logic.LE3.Out Signal: Latched Output (Q)
Logic.LE3.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE4.Gate Out Signal: Output of the logic gate
Logic.LE4.Timer Out Signal: Timer Output
Logic.LE4.Out Signal: Latched Output (Q)
Logic.LE4.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE5.Gate Out Signal: Output of the logic gate
Logic.LE5.Timer Out Signal: Timer Output
Logic.LE5.Out Signal: Latched Output (Q)
Logic.LE5.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE6.Gate Out Signal: Output of the logic gate
Logic.LE6.Timer Out Signal: Timer Output
Logic.LE6.Out Signal: Latched Output (Q)
Logic.LE6.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE7.Gate Out Signal: Output of the logic gate
Logic.LE7.Timer Out Signal: Timer Output
Logic.LE7.Out Signal: Latched Output (Q)
Logic.LE7.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE8.Gate Out Signal: Output of the logic gate
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