Eaton EMR-4000 - Page 985

EMR-4000 IM02602009E
Name Description
Logic.LE45.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE45.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE46.Gate Out Signal: Output of the logic gate
Logic.LE46.Timer Out Signal: Timer Output
Logic.LE46.Out Signal: Latched Output (Q)
Logic.LE46.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE46.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE46.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE46.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE47.Gate Out Signal: Output of the logic gate
Logic.LE47.Timer Out Signal: Timer Output
Logic.LE47.Out Signal: Latched Output (Q)
Logic.LE47.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE47.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE47.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE47.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE48.Gate Out Signal: Output of the logic gate
Logic.LE48.Timer Out Signal: Timer Output
Logic.LE48.Out Signal: Latched Output (Q)
Logic.LE48.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE48.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE48.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE49.Gate Out Signal: Output of the logic gate
Logic.LE49.Timer Out Signal: Timer Output
Logic.LE49.Out Signal: Latched Output (Q)
Logic.LE49.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE49.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In4-I State of the module input: Assignment of the Input Signal
www.eaton.com 985