NZM-XDMI-DPV1
(PROFIBUS-DPV1 Interface for
DMI)
132
11/04 MN01219002Z-EN
LS_Status[13] Bit 4 Unbalance
Bit 5 Not used
LS_Status[15] Bit 6 External power supply of the NZM
(via DMI or PC)
LS_Status[16] Bit 7 Supply voltage in order
Octet 3
1)
Status of the phases L1 and L2
2)
LS_Status[17] Bit 0 Phase L1: Normal range
LS_Status[18] Bit 1 Phase L1: Load rejection prewarning
LS_Status[19] Bit 2 Phase L1: Overload range 1
LS_Status[20] Bit 3 Phase L1: Overload range 2
LS_Status[21] Bit 4 Phase L2: Normal range
LS_Status[22] Bit 5 Phase L2: Load rejection prewarning
LS_Status[23] Bit 6 Phase L2: Overload range 1
LS_Status[24] Bit 7 Phase L2: Overload range 2
Octet 4
1)
Status of the phases L3 and N
conductor
2)
LS_Status[25] Bit 0 Phase L3: Normal range
LS_Status[26] Bit 1 Phase L3: Load rejection prewarning
LS_Status[27] Bit 2 Phase L3: Overload range 1
LS_Status[28] Bit 3 Phase L3: Overload range 2
LS_Status[29]
Bit 4 N-pole: Normal range
LS_Status[30] Bit 5 N-pole: Load rejection prewarning
LS_Status[31] Bit 6 N-pole: Overload range 1
LS_Status[32] Bit 7 N-pole: Overload range 2
Octet 5
1)
Tripping phase
2)
LS_Status[33] Bit 0 Trip via L1
LS_Status[34] Bit 1 Trip via L2
LS_Status[35] Bit 2 Trip via L3
Variable access
(example)
Data position Meaning
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