Eaton XN300 - Page 308

36 Interface module XN-322-2SSI
36.4 Memory layout
XN300 slice modules 02/24 MN050002EN Eaton.com 304
0x4102 0x8xxA
SUB 03
1 ConfigurationRegisterC
hannel2
Configuration registers
channel 2
(Default 0x20)
Bit 0-5 SSI Shift Register ; Length: 1-32 Bit
Bit
5 4 3 2 1 0
0 0 0 0 0 0 reserved
0 0 0 0 1 1 1-bit register
0 0 0 0 1 0 2-bit register
…
0 1 1 1 1 1 31-bit register
1 0 0 0 0 0 32-bit register
1 0 0 0 0 1 reserved
… reserved
1 1 1 1 1 1 reserved
0x0002
Bit 6 Read mode:
0: Single Read
1: Double Read
Bit 7 reserved
0x4103 0x8xxA
SUB 04
1 StateRegisterChannel2
Channel 2 status and
control register
Bit 0.1 SSI Shift Register Frequency
00 = 125 kHz
01 = 250 kHz
10 = 500 kHz
11 = 1 MHz
0x0003
Bit 2 0: Binary Data
1: Gray Code Decoding
Bit 3 SSI busy (1= busy) (read only)
Bit 4 Reserved
Bit 5 Error Clear (1 = clear error) (write)
Bit 6 Start with Sync (1= enable)
Bit 7 Continuous Sensor Read (1= enable)
CAN
Object
Index
Default
CAN
Mapping
EtherCAT
Object
Index
Size
(byte)
Local I/O
description
Local I/O
addresses