SEP 2005 MODEL 1000
INSTALLATION AND SETUP
3-78
3.4.4.15 Parallel I/O Configuration
Figure 3-33. Parallel I/O Configuration
The CPU (LPM/MCM-6117) utilizes the WinSystems WS16C48 ASIC high-density I/O chip
®
mapped at a base address of 120H. The first 24 lines are capable of fully latched event sensing with
sense polarity being software programmable. Two 50-pin connectors allow for easy mating with
industry standard I/O racks. The pin out for the two connectors are shown in Figure 3-34.
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