LQ-300 Service Manual
Operating Principles
2.3.10 Interface Circuit
Figure 2-21 shows the parallel interface arcuit block diagram. Data from the host computer is
latched within the gate array by STROBE signal. The gate array outputs XBUSY signal
automatically to stop the host computer from sending further data. The gate array reads the data
latched periodically with generating an interrupt.
The parallel I/F conforms to bidirectional parallel I/F
IEEE-P1284
level 1 nibble mode.
Parallel l/F
Gate
Array
(IC2)
127-134
DINO-7
39
~
-----
:
XSTROB
13
;
XB”SY
4
12
‘
----
4
~
------ XPE
14
4
------ XERR
4
15
------ XSLCT
4
L
‘
---
”
-
XSLIN
Fim.ue
2-22 shows
Figure 2-21. Parallel Interface Block Diagram
the serial
interface circuit block diagram. The serial interface conforms to
E&232D.
RXD
is data received by the serial 1/0 of th~CPU block from the host computer via
driver/receiver
IC4.
Data is transmitted to an input buffer in
IC1l
from the CPU. Printing starts
when a CR code is received or when the input buffer is filled.
+5V
Driver/Receiver
Serial
IIF
(IC4)
t
.,
TXD
4
.
D1OUT
DIIN
?
53
DTR
4
D20UT
D21N
~
52
RXD
F
RIIN
50
R1OUT
CTS
+
R21N
R20UT
54
RST
CPU (lCl)
P33
P32
P30
P34
Figure 2-22. Serial Interface Block Diagram
Rev.A
2-17
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