REV.-A
PRINCIPLES OF OPERATION
2.3.8 HOST INTERFACE
The host interface circuit is shown in Figure 2-69. STROBE pulses from the host computer pass through
the low-pass filter, consisting of R66 and C42, and flow into the STRB terminal. These pulses latch the parallel
data and set the BUSY signal HIGH, so that subsequent data transfer is inhibited. The gate array PINT
terminal is automatically output by the STRB signal to request a CPU interrupt. When the CPU receives
this interrupt request, it reads the data latched in the gate array.
LS07l8A)
R96 220K
Figure 2-69. Host Interface
LQ-510
2-63
To Next Page
Loading...
