PRINCIPLES OF OPERATION
REV.-A
2.3.2 RESET CIRCUIT
Figure 2-35 shows the reset circuit. The RESET signal generated here is sent to the RESET terminal of CPU
µPD7810HG (5B) and to connector CN2-13 (optional interface), and serves as a hardware initialization signal.
The RESET signal is output from the circuit when any of the following occur:
a. Power is turned on or off.
b. A module (font or identity) is mounted or removed.
c. The CPU itself generates a reset.
Note that initialization can occur whenever the host computer sends an INIT signal.
d. The INIT signal is input from either the host interface or an optional interface.
Figure 2-35. Reset Circuit
2-28
LQ-510
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