REV.-A
PRINCIPLES OF OPERATION
2.3.3 ADDRESS DECODER AND BANK REGISTER
The passages below describe the address decoder and bank register.
Address Decoder
This unit includes an address decoder in gate array E01 A05 (7A). The address decoder outputs a chip-select
signal to the internal PROM (6A), external PROM, 4MCG (3A), 1MCG (4A), external CG, RAM (5A), HEAD
gate array (1A) via address lines AB12 through AB15 and bank lines 7 and 6 (in the gate array). The chip
select for the CS, however, is generated in conjunction with the RD signal, and that of the RAM is generated
in conjunction with the ALE signal.
GA E01A05
(7A)
Address
Decoder
PROM(6A)
CE
EXTERNAL
PRGEX
b-m
PROM
Figure 2-40. Address Decoder
Firmware performs a soft-type check to determine whether an external PROM is attached. If an external
PROM is in place correctly, a LOW signal is sent to bit 7 of address F001 hex., enabling a switch-over to
the external program.
LQ-510
2-33
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