Epson PX-8 - Page 291

REV.-A
(1) Address Decoder
The address
decoder performs each register specification, chip select signal output control of
82C51 (2C) and SED1320 (7C), decoding of I/O read/write signals, etc.
,------,r;v:--I----l--l "-----cs (82C51)
OC
OE
I--------ll---I ~~--_ CS (SED 1320)
AB7
00
01
To
Address decoder
02
internal
AB3
03
registers
AB2
04
AB 1
ABO
05
06
RD
~--+--I~----IOR
10RQ
~--+-~ ~---IOW
WR
~--------~~------RSDLY
RS
Fig. 7-6
As shown in Figure 7 -6, the main CPU can directly select internal registers via four address lines.
The
CS signals of the 82C51 and SED1320 are also controlled by the I/O address decoder via this
registers.
7-20