Epson Stylus Pro 9500 - Page 19

EPSON Stylus Pro 9500 Revision A
Product Description SPECIFICATIONS 19
Note 1: *1 The return side means the twisted pair return and is connected to the signal ground
level. Furthermore, when interfacing, a twisted pair cable should definitely be used for each
signal and the return side should definitely connected. Also, use of a shielded cable and
connection to the chassis ground of the center machine and the printer, respectively are
effective countermeasures against noise.
Note 2: All the interface conditions are TTL level standard conditions. The rise and fall time of each
signal is 0.2 _s or less.
Note 3: There must not be any data transfer with disregard of the /ACKNLG or BUSY signals. (Data
transfer to this printer must be performed after the ACKNLG level is confirmed or when
BUSY is in the “LOW” state.)
Note 4: A horizontal line above the signal name sows a LOW active signal.
o Nibble Mode
Transmission mode: 8-bit Parallel
Synchronization: External Supply STROBE Pulse Signal
Handshaking: ACKNLG and BUSY Signal
Signal level: TTL level (IEEE-1284 level 1 device)
Connector: 57-30360 (Amphenol) or equivalent
Data transfer timing: Refer to IEEE-1284 specification
Data requests
: When the printer receives the hexadecimal values 00H
or 04H, the printer responds in the following manner:
00H: The printer enters reverse channel mode, allowing
data to be sent to the host.
04H: The printer sends the device ID to the host; the
device ID consists of the following strings
device ID:
<00H><4EH>
MFG: EPSON
CMD: ESCPL2, BDC
MDL: Stylus[SP]Pro[SP]9000;
CLS: PRINTER
DES: EPSON[SP]Stylus[SP]Pro[SP]9500
Note: [SP] equals space code 20H
Table 1-12. Parallel Interface Timing
Parameter Minimum Maximum
tsetup 500ns --
thold 500ns --
tstb 500ns --
tready 0 --
tbusy -- 500ns
treply --
tack Typical 2us
Tnbusy 0 --
tnext 0 --
Table 1-13. Connector Pin Assignments - Reverse Channel
Pin
No.
Signal Name
Return
Pin
In/
Out
Functional Description
1 HostClk 19 I
Host clock signal.
2-9 Data0-7 20-27 I
Each signal is at high level when data is
logical 1 and low level when data is logical 0.
10 PeriphClk 28 O Printer side clock signal.
11
PeriphAck/
PtrBusy
29 O
Printer side BUSY signal and data bit 3/7
in the reverse channel.
12 AckData Req 28 O
Acknowledge data request signal and
data bit 2/6 in the reverse channel.
13 Xflag 28 O
X-flag signal and data bit 1/5 in the
reverse channel.
14 HostBusy 30 I Host computer side BUSY signal.
15 NC (Not used.)
16 GND Ground for twisted pair return.
17 Chassis GND Chassis Ground
18 Logic-H O +5 V pull-up at 3.9 K Ohm.
19-30 GND Ground for twisted pair return
31 /INIT 30 I (Not used.)
32 /DataAvail 29 O
Data Available signal and data bit 0/4 in
the reverse channel.
33 GND Ground for twisted pair return