Ericsson M-RK - Phase-Lock-Loop Module (U2); Voltage-Controlled Oscillator (U5); VCTCXO Reference Oscillator (Z1); Logic Circuit

The VCO used to generate the receive and transmit
frequencies is locked to a stable VCTCXO reference
oscillator through a PLL. This feed-back loop divides the
VCO frequency down to a signal in the range of 3.5 MHz.
This signal is divided with a programmable divider to 6.25
kHz, and generates a VCO control signal by comparing the
6.25 kHz feedback with a 6.25 kHz signal derived by
dividing a 13.2 MHz (12.8 MHz for switchable models)
VCTCXO by 2112 (2048 for switchable models). As the
least-significant bit in the programming is changed, the VCO
is forced to change by 6.25 kHz.
Transmit audio fed into the synthesizer will be halved by
U4-2 in switchable radio units set for 12.5 kHz channel
spacing. This will limit voice deviation to a peak 2.25 kHz
and also halve CG/DCG encode deviation also.
The synthesizer circuitry is contained on two modules,
the VCO module U5 and the VCTCXO reference oscillator
module Z1.
Phase-Lock-Loop Module (U2)
The PLL module U2 contains a reference frequency, di-
vider, phase detector, and a programmable divider. The phase
detector dc voltage output signal is filtered with a passive
low-pass filter followed by a 6.25 kHz filter to reduce the
level of reference modulation on the VCO. This dc output
represents the error between the VCO frequency (phase) and
the reference (VCTCXO) and is applied to the VCO on fre-
quency. A lock-detect output is developed from pin 9 of U2.
The output is "AND"ed with the TX-PTT output from the
microcomputer to prevent transmission before the VCO is on
frequency.
Serial data from the microcomputer is shifted into the
PLL to set the division parameter which establishes the fre-
quency. A clock signal is provided on another input and the
data is latched with the enable input.
Voltage-Controlled Oscillator (U5)
The VCO uses a low-noise, high-gain transistor as the
basic oscillator. The resonant circuit, which determines the
frequency of oscillation, is formed by a high-Q SAW which
is used to set the center frequency at the factory. The output
of the VCO is coupled into a cascade amplifier which pro-
duces 0 dBm. The output of the RX-VCO amplifier is cou-
pled into the receive first double-balanced mixer circuit Z2
through amplifier Q103. The VCO amplifier output is also
connected to the input of TX-amplifier transistor Q104.
VCTCXO Reference Oscillator (Z1)
The Z1 oscillator module is self contained, fully tempera-
ture compensated and operates at a frequency of 13.2 MHz
(12.8 MHz for switchable models). The oscillator also has
modulation capability. Frequency is adjusted by a trimmer
while monitoring the transmit circuit output at the antenna
jack.
LOGIC CIRCUIT
The logic circuit consists of control circuits and audio
circuits (Figures 5 thru 8). Physically, this circuit consists of
two circuit board as follows:
• Control Board Assembly
• LED Flex Assembly (M-RK I)
• LCD/KB flex Assembly (M-RK II & Scan)
Control Board Assembly
The Control board consists of the following circuits (re-
fer to Figures 5 thru 8):
• CMOS Microprocessor (U1, U2)
• E
2
PROM (U6)
• Flash E
2
PROM (U4)
• Custom CMOS DSP Chip (U3)
• Custom CMOS ASP Chip (U7)
• CMOS Inverters (U12)
• CMOS OR gates (U15)
• CMOS SRAM (U5)
• Audio Amplifier (U11)
• 5 volt Regulator (U9,10)
• Semi-custom CMOS ADSP chip (U17) for Aegis
models
Microcomputer
The main microcomputer circuit in this radio consists of
microprocessor, H8/532 (U2), 2K x 8 E
2
PROM (U6), 128K
(upgraded to 512K in later models) x 8 flash EPROM (U4),
8K (upgraded to 32K in later models) x 8 RAM (U5), and
custom DSP (U3). This circuitry runs at a 9.8304 MHz rate
determined by crystal Y1 and controls the radio through a
second microprocessor H8/330 (U1). This microprocessor
(U1) runs at an 4.9152 MHz rate. The 4.9152 MHz rate is
determined by DSP (U3).
LBI-38735
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