Basic Node
10046
SPI
TDM
TDM Bus
High Speed
Bus
PCI Bus
SPI Bus
Power
Power Bus
Secondary
voltages
High
Speed
Control and
Supervision
Inverse
Multiplexers
Ethernet
1000BASE-TX
1000BASE-TX
10/100/1000BASE-T
10/100/1000BASE-T
nxE1
nxE1
nxE1
nxE1
nxE1
nxE1
Figure 35 Block diagram for ETU3
3.7.4.1.1 TDM
This block interfaces the TDM bus by receiving and transmitting the E1s used
to carry Ethernet traffic.
3.7.4.1.2 Inverse Multiplexers
Each inverse multiplexer converts one Ethernet connection into nxE1, where
n≤48, transmitted to and received from the TDM block. There is a total of 48
E1s for three IM groups.
3.7.4.1.3 Ethernet
This block provides the unit’s external Ethernet interfaces. For ETU2 each
interface is linked to one inverse multiplexer, and for ETU3 each interface is
linked to the High Speed Bus.
For ETU2, the Ethernet Traffic function offers 8 priority queues in both directions
to/from the Ethernet ports. The mapping follows IEEE 802.1D 2004 strict priority
41
12/221 02-CSH 109 32/1-V1 Uen A 2008-03-14