Furuno FAR-2127 - Page 377

7.3 Processor Unit: RPU-013
7-33
The figure below shows the overview of functions of FPGA. See page.7-37 for specific
signal processing.
Fig. 7.3.6 Block diagram of FPGA
Echo detct
FTC processing (Auto Rain)
Sampling
Selcter Selcter
QV echo
Echo select
ACQ
Tracking
CPA/TCPT
IR processing
ARPA CPU
DRW CPU
AD Con.
FULL LOG Video
SEM LOG Video
ARPA test echo
ARPA
test echo
OP video signal
88 88 8
Encode
Decode
Trigger GEN
(Jamming)
PLL
UART
(I/O)
TX TRG
EXT TRIG
EXT TRIG
HD
HD
HD
BP
BP
BP(8192)
EXT BP
EXT HD
SAMPL TRIG
SAMPL TRIG
RF TXD
RF RXD
From/To
RFC p.c.b
To
External Display
From
External Radar
RS-422
RS-422
Test echo/HD/BP/TRIG
- LAN I/F - Inter SW - TX data GEN - RX data
Video Contrast
ES
AZ counter
GYRO data
Echo data processing (Correlation)
Trailing data processing
Display data processing
Echo data memory
Trailing data memory
Display data memory
RO-XY converter & ADD. GEN
RO-XY converter & ADD. GEN
RO-XY converter & ADD. GEN
Graphic data ADD. GEN
Graphic data memory
NET-100
(LAN I/F)
Display
priority
- Coler palette
Display color
- Brilliance
Sync sig. GEN
Closs cursor
processing
Graphic data processing
Graphic data
processing
MAIN CPU
Closs cursor
data
Graphic data
SPU FPGA
Echo FPGA
DRW FPGA
Main CONT
DVI driver DVI driver
Dot
CLK
108MHz