5.3 Block Description
5-9
Fig. 5.3.3 Block Diagram: CPU block
Table 5.3.2 Memory contents
Memory Memory description
ROM ROM integrating U8 Program storage
SRAM U10
All received messages and setup menus,
work memory
DRAM U5 Memory for display, work memory
CPU RAM ROM integrating U8 CPU work memory
EEPROM U13
When a battery for the SRAM (U10) back up is
replaced, all the setup menus stored here are
transferred to the SRAM.
Setting data is updated every hour.
CPU
M32171F4VFP
EEPROM
SRAM
DRAM
(32kx8bits)
Reset
BATT
LCD
Controller
LCD
Data BUS
Data BUS
Backup
D/A
Contrast
Beep SP
RS232C I/F
RS485 I/F
(ISO)
RS485 I/F
ALARM BZ
MOS RL
NAVTESX
Receiver
KEY x 10
RESET n
RESET n
U8
U13
BT1
U11
U10
U4 U5
U17
U2
U28
U16/19
U7
(512kB)
(512kB)
Key scan
Source
Key scan
Retrn
Key
Back light
LCD
Back light
CR1/4/9/
19/13/10
Printer SD/RD
INS TD-A/B, RD-A/B
T/RxD 0
RxD 2
TxD 1
490 DEC IN
518 DEC IN
RCV TX0
RCV TX1
LS1
FDK
ALARM
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