GE Multilin F650 - Page 248

GEK-113000T F650 Digital Bay Controller C-23
APPENDIX C C.2 FACTORY DEFAULT CONFIGURATION
C
PH IOC3 HIGH A BLK
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR3 A OP NOT
LATCHED VIRT IP 1
PH IOC3 HIGH B BLK
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR3 B OP NOT
LATCHED VIRT IP 1
PH IOC3 HIGH C BLK
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR3 C OP NOT
LATCHED VIRT IP 1
PH IOC1 LOW A BLK
GROUP 1 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR1 A OP NOT
LATCHED VIRT IP 2
PH IOC1 LOW B BLK
GROUP 1 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR1 B OP NOT
LATCHED VIRT IP 2
PH IOC1 LOW C BLK
GROUP 1 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR1 C OP NOT
LATCHED VIRT IP 2
PH IOC2 LOW A BLK
GROUP 2 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR2 A OP NOT
LATCHED VIRT IP 2
PH IOC2 LOW B BLK
GROUP 2 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR2 B OP NOT
LATCHED VIRT IP 2
PH IOC2 LOW C BLK
GROUP 2 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR2 C OP NOT
LATCHED VIRT IP 2
PH IOC3 LOW A BLK
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR3 A OP NOT
LATCHED VIRT IP 2
PH IOC3 LOW B BLK
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR3 B OP NOT
LATCHED VIRT IP 2
PH IOC3 LOW C BLK
GROUP 3 BLOCKED
CONT IP_F_CC2 (50P BLOCK)(CC2)
PHASE DIR3 C OP NOT
LATCHED VIRT IP 2
SETPOINT>RELAY CONFIGURATION>PROTECTION ELEMENTS
PROTECTION ELEMENT SOURCE SIGNAL LOGIC SOURCE LOGIC