GE PCIE-5565PIORC* User Manual

GE
Intelligent Platforms
Publication No: 500-9367875565-000 Rev. A
Hardware Reference
PCIE-5565PIORC*
Ultrahigh Speed Fiber-Optic Reflective Memory
with Interrupts
THE PCIE-5565PIORC IS DESIGNED TO MEET THE EUROPEAN UNION (EU) RESTRICTION OF HAZARD-
OUS SUBSTANCE (ROHS) DIRECTIVE (2002/95/EC) CURRENT REVISION.
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GE PCIE-5565PIORC* Specifications

General

Form Factor	PCI Express
Operating Temperature	0°C to 55°C
Manufacturer	GE Intelligent Platforms
Model	PCIE-5565PIORC
Category	PCI Card

Summary

Document History

Overview

PCI Express Compliance

Vendor and Device Identification

Subsystem Vendor ID and Subsystem ID

Block Diagram

References

Organization

Safety Summary

General Safety Precautions

Covers essential safety measures for system operation, service, and modifications.

Warnings, Cautions and Notes

1 Handling and Installation

1.1 Unpacking Procedures

Describes the steps for safely unpacking the product and inspecting for damage.

1.2 Handling Precaution

Provides precautions for handling sensitive components to prevent ESD damage.

1.3 Switch S1 and S2 Configuration

1.4 Physical Installation

1.5 Front Panel Description

1.5.1 LED Description

1.6 Cable Configuration

1.6.1 Connector Specification (Singlemode and Multimode)

Specifies the connector type and its characteristics for fiber-optic cables.

2 Theory of Operation

2.1 Basic Operation

Describes how nodes communicate and data is transferred in the Reflective Memory network.

2.2 Front Bezel LED Indicators

Details the function and meaning of the LEDs on the front panel of the board.

2.3 RFM-5565 Register Sets

2.4 Reflective Memory RAM

2.5 Interrupt Circuits

2.6 Network Interrupts

2.7 Redundant Transfer Mode of Operation

2.8 Rogue Packet Removal Operation

3 Programming

3.1 PCI Configuration Registers

Details the standard PCI configuration registers and their functions.

3.2 Local Configuration Registers

3.3 RFM Control and Status Registers

3.3.1 Board Revision Register

Describes the 8-bit register for board revision or model numbers.

3.3.2 Board ID Register

Details the 8-bit register containing a unique code for RFM-5565 boards.

3.3.3 Board Revision Build Register

Describes the 16-bit register for the build number and PCI memory window size.

3.3.4 Node ID Register

Explains the 8-bit register reflecting the onboard switch S2 setting for node ID.

3.3.5 Local Control and Status Register 1

Details the 32-bit register for Reflective Memory control and status bits.

3.3.6 Local Interrupt Control Registers

Local Interrupt Enable Register

3.3.7 Network Target Data Register

3.3.8 Network Target Node Register

3.3.9 Network Interrupt Command Register

3.3.10 Interrupt 1 Sender Data FIFO

3.3.11 Interrupt 1 Sender ID FIFO

3.3.12 Interrupt 2 Sender Data FIFO

3.3.13 Interrupt 2 Sender ID FIFO

3.3.14 Interrupt 3 Sender Data FIFO

3.3.15 Interrupt 3 Sender ID FIFO

3.3.16 Interrupt 4 Sender Data FIFO

3.3.17 Interrupt 4 Sender ID FIFO

3.4 Example of a Block DMA Operation for RFM-5565

3.5 Example of a Scatter-Gather DMA Operation for RFM-5565

3.6 Example of a PCI PIO Sliding Window Operation for RFM-5565

3.7 Example of Network Interrupt Handling

3.7.1 Setup

Outlines the setup steps required to generate a PCI interrupt from network interrupts.

3.7.2 Servicing Network Interrupts

Describes the procedure for servicing network interrupts and handling associated data.

Maintenance

Maintenance Prints

Compliance Information

FCC Part 15

FCC Class A

Specifies the limits for Class A digital devices and potential interference.

Canadian Regulations