5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPC_CLK0
-INTR_ALERT
LPC_CLK1
RTC_XO
RTC_XI
RTC_XO
RTC_XI
-LDT_STOP
-CPURST
-PROCHOT_CPU
PCLK1 LPC33
PCICLK2
PCICLK1
PCLK3
PCLK2
-PPCIRST
AD11
AD4
AD3
AD23
AD20
AD31
AD1
AD5
AD12
AD9
AD18
AD22
AD8
AD10
AD19
AD27
AD16
AD15
AD7
AD0
AD21
AD29
AD2
AD13
AD6
AD14
AD24
AD28
AD26
AD17
AD25
AD30
-C_BE1
-C_BE3
-C_BE2
-C_BE0
-PCI_CLKRUN
-PLOCK
-REQ0
-REQ1
-REQ2
-REQ4
-REQ3
-GNT4
-GNT1
-GNT0
-FRAME
-DEVSEL
-IRDY
-TRDY
PAR
-STOP
-PERR
-SERR
-INTA
-INTB
-INTD
-INTC
SERIRQ
LAD0
-LDRQ1
LAD3
LAD1
LAD2
-LDRQ0
-LFRAME
RTC_CLK
VBAT_2
RTCVDD
LPC_CLK1
LPC_CLK0
RTC_CLK
-PCI_CLKRUN
PCLK3
PCLK2
VCC_SB
VCC18
VCC3
VCC3
RTCVDD
RTCVDD
3VDUAL
RTCVDD
3VDUAL
VCC3
VCC
VCC3
VCC3
VCC_SB
-A_RST<24>
A_TX2P<9>
A_TX2N<9>
A_TX3P<9>
A_TX3N<9>
A_TX0P<9>
A_TX0N<9>
A_TX1P<9>
A_TX1N<9>
A_RX2P<9>
A_RX2N<9>
A_RX3P<9>
A_RX3N<9>
A_RX0P<9>
A_RX0N<9>
A_RX1P<9>
A_RX1N<9>
SBSRC_CLKN<12>
SBSRC_CLKP<12>
CPU_PG_SB<6>
-LDT_STOP<6,10>
-CPURST<6,10>
ALLOW_LDTSTOP<10>
-PROCHOT_CPU<6>
PCICLK2 <18>
PCICLK1 <18>
LPC33 <24>
-PPCIRST <18>
AD[0..31] <18>
-C_BE1 <18>
-C_BE3 <18>
-C_BE2 <18>
-C_BE0 <18>
-REQ0 <18>
-REQ3 <18>
-REQ2 <18>
-REQ1 <18>
-GNT0 <18>
-GNT1 <18>
-FRAME <18>
-DEVSEL <18>
-IRDY <18>
-TRDY <18>
PAR <18>
-STOP <18>
-PERR <18>
-SERR <18>
-PLOCK <18>
-REQ4 <18>
-INTC <18>
-INTB <18>
-INTA <18>
-INTD <18>
LAD0 <24>
LAD1 <24>
LAD2 <24>
LAD3 <24>
SERIRQ <24>
-LDRQ0 <24>
-LFRAME <24>
VBAT<24>
-GNT4 <18>
Title
Size Document Number Rev
Date: Sheet of
GA-880GM-D2H 1.32
ATI SB710 PCIE/PCI/CPU/LPC
Custom
13 30Thursday, August 05, 2010
Title
Size Document Number Rev
Date: Sheet of
GA-880GM-D2H 1.32
ATI SB710 PCIE/PCI/CPU/LPC
Custom
13 30Thursday, August 05, 2010
Title
Size Document Number Rev
Date: Sheet of
GA-880GM-D2H 1.32
ATI SB710 PCIE/PCI/CPU/LPC
Custom
13 30Thursday, August 05, 2010
PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO U600
Note: LDT_PG, LDT_STP# & LDT_RST# are OD
and require a PU to the CPU I/O rail. They are
also in the S5 domain to prevent glitching at
power up.
S.B HEATSINK
20mil20mil
20mil
NOT ADD ICT FOR RTCVDD PIN
CLEAR CMOS
NORMALOPEN
CLR_CMOS
SHORT
WATCHDOG TIMER
ON NB_PWRGD
ENABLED
PCLK2
WATCHDOG TIMER
ON NB_PWRGD
DISABLED
PULL
HIGH
PULL
LOW
DEFAULT
PCLK3
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAPS
DEFAULT
LPC_CLK0 LPC_CLK1
CLKGEN
ENABLED
CLKGEN
DISABLED
DEFAULT
PULL
HIGH
PULL
LOW
EMI 20071107
AOD Extreme
IMC
DISABLED
IMC
ENABLED
DEFAULT
BIOS after boot setting
EC AOD-ACC
R251 22/4R251 22/4
C224 0.1U/4/X7R/16V/KC224 0.1U/4/X7R/16V/K
CR2032
+
BAT
CR2032
CR2032
+
BAT
CR2032
R121 8.2K/4/1R121 8.2K/4/1
PCI EXPRESS INTERFACE
Part 1 of 5
SB700
PCI INTERFACE
LPC
RTC
CPU
RTC XTAL
PCI CLKS
CLOCK GENERATOR
U2A
SB710/FCBGA528/A14/[10HB1-06B710-11R]
PCI EXPRESS INTERFACE
Part 1 of 5
SB700
PCI INTERFACE
LPC
RTC
CPU
RTC XTAL
PCI CLKS
CLOCK GENERATOR
U2A
SB710/FCBGA528/A14/[10HB1-06B710-11R]
A_RST#
N2
PCIE_RX2P
R20
PCIE_RX2N
R21
PCIE_RX3P
R18
PCIE_TX3N
T22
PCIE_TX3P
T23
PCIE_TX2N
U24
PCIE_TX2P
U25
PCIE_RX1P
U19
PCIE_RX1N
V19
PCIE_RX0P
U22
PCIE_RX0N
U21
PCIE_TX1N
V25
PCIE_TX1P
V24
PCIE_TX0N
V22
PCIE_TX0P
V23
PCIE_RCLKP/NB_LNK_CLKP
N25
PCIE_RCLKN/NB_LNK_CLKN
N24
PCIE_CALRP
T25
PCIE_CALRN
T24
PCIE_PVDD
P24
GPP_CLK1N
L19
X1
A3
X2
B3
VBAT
B2
GPP_CLK0N
J18
GPP_CLK2P
M19
ALLOW_LDTSTP
F23
CPU_HT_CLKN
M18
GPP_CLK2N
M20
SLT_GFX_CLKP
M23
CPU_HT_CLKP
P17
LDT_RST#
G24
PCICLK0
P4
PCICLK1
P3
PCICLK2
P1
PCICLK3
P2
PCIRST#
N1
CBE0#
W2
CBE1#
U7
CBE2#
AA7
CBE3#
Y1
FRAME#
AA6
DEVSEL#
W5
IRDY#
AA5
TRDY#
Y5
PAR
U6
STOP#
W6
PERR#
W4
REQ0#
AC3
REQ1#
AD4
REQ2#
AB7
REQ3#/GPIO70
AE6
GNT0#
AD2
GNT1#
AE4
GNT2#
AD5
GNT3#/GPIO72
AC6
SERR#
V7
CLKRUN#
AD6
LAD0
H24
LAD1
H23
LAD2
J25
LAD3
J24
LFRAME#
H25
LDRQ0#
H22
SERIRQ
V15
PCICLK4
T4
LPCCLK0
G22
LPCCLK1
E22
AD0
U2
AD1
P7
AD2
V4
AD3
T1
AD4
V3
AD5
U1
AD6
V1
AD7
V2
AD8
T2
AD9
W1
AD10
T9
AD12
R7
AD13
R5
AD14
U8
AD15
U5
AD16
Y7
AD17
W8
AD18
V9
AD19
Y8
AD20
AA8
AD21
Y4
AD22
Y3
AD23
Y2
AD24
AA2
AD25
AB4
AD26
AA1
AD27
AB3
AD28
AB2
AD29
AC1
AD30
AC2
AD31
AD1
AD11
R6
REQ4#/GPIO71
AB6
GNT4#/GPIO73
AE5
LDRQ1#/GNT5#/GPIO68
AB8
GPP_CLK1P
L20
RTCCLK
C3
PCIE_RX3N
R17
INTE#/GPIO33
AD3
INTF#/GPIO34
AC4
INTG#/GPIO35
AE2
INTH#/GPIO36
AE3
LOCK#
V5
PCIE_PVSS
P25
PCICLK5/GPIO41
T3
BMREQ#/REQ5#/GPIO65
AD7
NB_HT_CLKP
M24
LDT_PG
F22
LDT_STP#
G25
GPP_CLK3N
P22
INTRUDER_ALERT#
C2
NB_DISP_CLKP
K23
25M_48M_66M_OSC
L18
GPP_CLK0P
J19
NB_HT_CLKN
M25
SLT_GFX_CLKN
M22
GPP_CLK3P
N22
25M_X1
J21
25M_X2
J20
NB_DISP_CLKN
K22
PROCHOT#
F24
R283 33/4R283 33/4
C226 0.1U/4/X7R/16V/KC226 0.1U/4/X7R/16V/K
C93
18P/4/NPO/50V/J
C93
18P/4/NPO/50V/J
BAT54C/SOT23/200mA
Q4
BAT54C/SOT23/200mA
Q4
C218 0.1U/4/X7R/16V/KC218 0.1U/4/X7R/16V/K
R253 22/4R253 22/4
R241 2.05K/4/1R241 2.05K/4/1
BC816
10U/8/X5R/6.3V/K
BC816
10U/8/X5R/6.3V/K
C221 0.1U/4/X7R/16V/KC221 0.1U/4/X7R/16V/K
R124 8.2K/4/1R124 8.2K/4/1
R255 100K/4/1R255 100K/4/1
R169 8.2K/4/1R169 8.2K/4/1
R163 1K/4/1R163 1K/4/1
C219 0.1U/4/X7R/16V/KC219 0.1U/4/X7R/16V/K
R254 22/4R254 22/4
X4
32.768K/12.5p/20ppm/TF38/35K/D
X4
32.768K/12.5p/20ppm/TF38/35K/D
1 2
3 4
BAT
BAT-SK/BK/P/S/D/SN
BAT
BAT-SK/BK/P/S/D/SN
12
R76 8.2K/4/XR76 8.2K/4/X
R161 22/4R161 22/4
BC21
0.1U/4/X7R/16V/K
BC21
0.1U/4/X7R/16V/K
1U/6/Y5V/10V/Z
BC22
1U/6/Y5V/10V/Z
BC22
C222 0.1U/4/X7R/16V/KC222 0.1U/4/X7R/16V/K
R125 8.2K/4/XR125 8.2K/4/X
C92
18P/4/NPO/50V/J
C92
18P/4/NPO/50V/J
R115 8.2K/4/1R115 8.2K/4/1
R165 33/4R165 33/4
CLR_CMOS
PH/1*2/BK/2.54/VA/D
CLR_CMOS
PH/1*2/BK/2.54/VA/D
R2710 8.2K/4/1R2710 8.2K/4/1
R172 8.2K/4/XR172 8.2K/4/X
R160 22/4R160 22/4
X4
SHW/D0.64*5.08*6.74
X4
SHW/D0.64*5.08*6.74
R171 8.2K/4/1R171 8.2K/4/1
SB_HS
SB_HS/[12SP2-030005-42R_12SP2-030005-41R_12SP2-030005-43R]
SB_HS
SB_HS/[12SP2-030005-42R_12SP2-030005-41R_12SP2-030005-43R]
1
1
2
2
RB 1K/4/1RB 1K/4/1
R126 8.2K/4/1R126 8.2K/4/1
C159
1n/4/X7R/50V/K
C159
1n/4/X7R/50V/K
R226 562/4/1R226 562/4/1
R166
20M/4
R166
20M/4
C220 0.1U/4/X7R/16V/KC220 0.1U/4/X7R/16V/K
BC783
0.1U/4/X7R/16V/K
BC783
0.1U/4/X7R/16V/K
BC815
1U/6/Y5V/10V/Z
BC815
1U/6/Y5V/10V/Z
R127 8.2K/4/XR127 8.2K/4/X
C227 0.1U/4/X7R/16V/KC227 0.1U/4/X7R/16V/K
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