Harman Kardon JBL Link 20 - BOOT STRAP OPTION; STRAP OPTION

Harman Lifestyle
HARMAN I NTERNA TIO NAL
Shenzhen, Guangdong, China
SIZE
TITLE
REV.
SHEET OF
SCALE:
B
DRAWING NO.
CREATED
CHECKED
A
B
C
D
A
B
C
123
4
123
4
D
DATE
CAD FI LE:
REVISION HISTORY
REV ECO CHECKED DATE
PROPRIETARY INFORMATION - THESE DO CUMEN TS AND THE INFORMATION
CONTAI NE D THERE IN ARE PROPRIETARY AND ARE NOT TO BE REPRODUCED
OR DIS CLOS E D TO OTHERS FOR MA NUF A CTURE OR ANY OTHER PURPOS E EXCEPT
THOSE SPECIFICALLY AUTHORIZED IN WRI T IN G BY HARMA N I NTERNA TIONA L
NAME
Strap
710
R62
NC
BG2CDp_SD0_DAT0
BG2CDp_SD0_DAT1
BG2CDp_SD0_DAT2
BG2CDp_SD0_DAT3
BG2CDp_SD0_CMD
R63
NC
R64
NC
R65
NC
PWR_VDDIO5
R66
NC
4.7K
R311
NC
PWR_3V3
BG2CDp_SPI1_SDO
4.7K
R23
NC
BG2CDp_NAND_CE0n
GND
4.7K
R24
NC
PWR_3V3
BG2CDp_NAND_WPn
4.7K
R34
NC
BG2CDp_SPI1_SS0n
GND
4.7K
R26
NC
PWR_3V3
BG2CDp_SPI1_SCLK
4.7K
R38
NC
BG2CDp_PERIF_OFFn
pwrCntlBy ps : 1: Enable pow er. 0: Di senable powe r. Default 0
GND
GND
PWR_3V3
C129
0.1uF
R59
10K
RESET#
25V
C130
5.6PF
25V
C131
5.6PF
GND
5%
R61
10 OHM
5%
R60
10 OHM
STRAP OPTION
BYPASS SYS/MEM/CPU PLL 0: Do not bypass PLLs 1: Bypass PLLs Default:1
PWRDWN SY S/M EM /CPU PLL 0: Do not PWRDWN PLLs 1: PWRDWN PLLs Default: 1
cpuRstByps 0: Enable rese t logic inside cpu parti ti on 1: Bypass reset logic inside cpu partition Default:0
software_strap[1] dafault:0
NAND1.8EN AB LE Default:0 = 3.3V
BootS rc[1:0] ? A
DDR ? TYPE
2'b00 ? FF80-0000' h ? SPI -Secure Boot
2'b01 ? FF80-0000' h ? NAND FLASH Boot * Default
2'b11 ? F000-
0000' h ? SPI-Clear Boot
boot _src[1:0 ] See table below (Updated for BG2 CD)
SDO_CLK = 0 ? USB boot
SOC RESET
GND
PWR_3V3
C133
0.1uF
BOOT STRAP OPTION
PWR_3V3
2017/4/20
2017/4/20
CLKI
CLKO
13
2
4
Y1
S2SM25.0000F15E22
C10
4.7uF
single point to GND.
R86
4.7K
R88
4.7K
R93
NC
R85
NC
PWR_VDDIO8
GND
BG2CDp_NAND_ALE
BG2CDp_NAND_CLE
boot_src[1]:CPU Boot Soure[1]
boot_src[0]:CPU Boot Souce[0]
boot_src[1.0]=01:ROM boot from NAND
VDD
3
/RESET
2
GND
1
U5
RT9818B-29GU3