Supply Fault logic outputs LOW until all Controller power
supply voltages are normal. This allows time for other transmit-
ter supplies to reach normal voltages and clear the Type 1 fault
induced “off” command before a “power level latch” inhibit is
removed.
P.10.3.1 “Fast On”
When a supply fault occurs, the output of U49-2 goes HIGH
and charges capacitor C71 through diode CR12 and a 100 Ohm
resistor R37. When the rising voltage across C71 goes abovethe
threshold of inverting Schmitt trigger, U49-4 goes LOW.
P.10.3.2 “Slow Off”
When the supply fault clears, the output of U49-2 goes LOW
and capacitor C71 discharges through R38. Inverting Schmitt
trigger U49-4 remains LOW until the voltage across C71 drops
below the trigger threshold again. This provides a “delay off”
for the Data Clear and Supply Fault logic signals.
P.10.4
“Data Clear-L” signal
Two inverters, U49-6/10, are used together as a non-inverting
logic buffer to provide a “Data Clear” signal to the Analog Input
Board. The “Data Clear-L” signal will clear all BCD informa-
tion in the power control latches.
P.10.5
“Supply Fault-L” signal to LED Board
The “Supply Fault-L” signal is sent to the LED Board at J8-11
(sheet 1 of the Controller schematic). The signal is used to
trigger the “VSWR Self-Test”circuit and to clockany overloads
present on AC restart.
P.11 Analog Metering Buffer/Drivers
Sheet 6 of the Controller schematic diagram includes opera-
tional amplifier buffer/drivers, and voltmeter multiplier resis-
tors, for analog metering. All buffer/drivers are configured as
voltage followers, with gain of 1, high impedance inputs, and
low impedance outputs.
P.11.1
Forward and Reflected Power Metering
Signals for the front panel and remote metering are supplied by
U65. Input signals for these circuits come from the Output
Monitor through the LED Board. Outputs of these circuits go
to the Switch Board/Meter Panel and the External Interface.
P.11.2
VSWR Detector Null Metering (U64)
Four voltage followers buffer the Output Network VSWR Null
and Load Network VSWR Null signals. U64-14 and U64-1
drive the front-panel multimeter on the transmitter, and voltage
multiplier resistors R67 and R68 are in series with the op-amp’s
low impedance output. U64-7 and U64-8 drive the external
interface, and have voltage dividers at their outputs.
P.11.3
Supply Volts Metering (U63C)
Only one section of U63 is used, and is shown on sheet 5. This
voltage follower drives both the front panel multimeter,through
voltmeter multiplier resistor R54, and the External Interface,
through voltage divider R70 and R78
P.12 AC Power Recycle (Recycle “On”
After Power Failure)
When primary AC is restored after a powerfailure, the transmit-
ter will automatically recycle ON at the same power level and
operating condition as before the power failure, unless the
power failure was long enough to discharge the +5B “memory
back-up supply.”
The AC Power Recycle function can be divided into two parts:
a. First, the latched power level generates a turn-on request
when an “inhibit” is released.
b. Second, when power is first applied to the transmitter, a
fault-generated “off” command is generated but is not
latched because the latch “clock” signal is inhibited.
P.12.1
Generates Turn-on Request
The power level at the time of the power failure is still latched
in power level latch U40. When all supplies are up to normal
voltage and the “Fault” input clears, the “inhibit” inputs of the
three power level inhibit gates go high. The output of the gate
for the power level latched in U40 (HIGH, MEDIUM or LOW)
goesHIGH, and generatesa“Turn-OnRequest”to U56-2. When
the “Supply Fault” delay returns U56-3 to HIGH, the transition
begins the step-start sequence.
P.12.2
Inhibited OFF command
When AC power comes back on, various regulated power sup-
plies on printed circuit boards generate “Supply Fault” outputs
until the supplies are within 10% of their normal output voltage.
As long as any “Supply Fault” signal is present, a “Type 1 Fault”
signal input is present to the turn-on/turn-off control logic.
This “fault” also generates an OFF command, but this is not
clocked into the power level latch because the “clock” pulse is
inhibited, by the delayed “Supply Fault.”
Until the transmitter power supplies come up to normal voltage,
“Supply Fault”logic outputs generatea Type 1 Fault. The“Type
1fault” generates an “OFF” command to Q5-6 from the output
ofU51-8.The commandis decodedand sent to powerlevellatch
U40. However, it is not latched because the “Clock” input to the
latch is inhibited until approximately five seconds after the
Controller regulator outputs reach their normal voltages.
The “OFF” command is INHIBITED when pins 1 and 2 of gate
U57 are held LOW, by the “Supply Fault-L” signal. This forces
thelatch’s outputHIGH sothat the clocksignalis inhibited from
latching U40.
P.12.3
Supply Fault-L, Five second “Off” delay
Input commands, including the fault-induced “Off” command,
cannot be latched during the five-second delay. During this
delay, the outputs of digital Power Data latches U17 and U18
on the Analog Input Board are also held at zero by the “Data
Clear-L” signal generated from the “Supply Fault-L.” The PA
Supply should be ON by the end of this five-second delay. The
poweroutput is still zero, and a“Data Strobe”is generatedwhen
the “Data Clear-L” signal is removed.
Section P - Controller (A38)
Rev. S: 05-02-97 888-2297-002 P-19
WARNING: Disconnect primary power prior to servicing.
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