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Heathkit IM-4100 - Page 56

Heathkit IM-4100
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Hegeep
(gears)
CIRCUIT
DESCRIPTION
Refer
to
the
Schematic
Diagram
and
the
Block
Diagram
while
you
read
this
‘“‘Circuit
Description.”
The
following
“Theory
of
Operation’
contains
a
general
description
of
the
circuits.
The
remaining
sections
describe
each
circuit
in
detail.
THEORY
OF
OPERATION
The
signal
to
be
counted
is
applied,
through
the
input
attenuator
and
impedance
converter
to
the
Schmitt
trigger.
There
the
signal
is
‘‘squared’’
and
applied
to
the
GATE.
During
the
time
the
pulse
from
the
time
base
scaler
(GATE
pulse)
is
also
present
at
the
GATE,
the
GATE
is
open
and
the
frequency
is
counted
by
the
following
decade
counters.
After
the
GATE
is
closed,
at
the
end
of
the
GATE
pulse,
the
“count”
in
the
decade
counters
is
transferred
to
the
memories
by
the
transfer
pulse.
At
this
time,
proper
segments
of
the
display
units
turn
on
and
the
frequency
is
displayed.
The
reset
pulse
then
clears
the
decade
counters
so
they
are
ready
for
the
next
time
the
GATE
is
open.
The
duration
of
the
GATE
pulse
is
determined
by
the
position
of
the
POWER/TIME
BASE
switch.
The
pulse
is
of
one-second
duration
in
the
kHz
position
and
of
one
millisecond
duration
in
the
MHz
position.
The
input
to
1C13
converts
either
the
time
base
or
the
input
period
to
a
GATE
“ON”
time,
depending
on
the
position
of
the
Mode
switch.
By
counting
the
input
signal
gated
by
the
time
base
signal,
frequency
is
displayed.
By
counting
the
time
base
signal
gated
by
the
input
signal,
period
is
displayed.
In
the
totalize
mode,
the
Counter
simply
counts
the
input
signal
without
any
gating.
INPUT
CIRCUIT
AND
SCHMITT
TRIGGER
The
input
signal
is
applied
to
an
input
circuit
that
consists
of
a
switchable
voltage
divider
(R1,
R2,
R3)
that
is
frequency
compensated
by
C1,
C2,
and
C3.
The
signal
is
then
coupled
through
C4
and
R4
to
D1
and
D2,
which
provide
over-voltage
protection
for
Q1.
Transistors
Q1
and
Q2
are
direct
coupled
with
100%
negative
feedback.
These
transistors
provide
wide
bandwidth,
high
input
impedance,
low
output
impedance,
and
gain
of
one.
IC1C
and
IC1A
then
amplify
the
signal
to
the
input
limits
of
1C1B,
which
is
wired
as
a
Schmitt
trigger.
1C1B
drives
Q3
and
O4,
which
translates
the
signal
to
TTL
(Transistor-Transistor-Logic)
levels
and
makes
the
signal
compatible
with
the
remaining
logic
circuitry.
10
MHz
CLOCK
AND
SCALER
A
10
MHz
crystal
and
gates
B
and
C
of
IC26
form
a
TTL-compatible
clock.
Capacitors
C7,
C8,
and
C9
provide
the
proper
capacitive
load
for
the
crystal,
and
C7
is
variable
to
allow
you
to
precisely
calibrate
the
oscillator.
Resistors
R21, R22,
and
R23
assure
efficient
starting
of
the
oscillator.
Gate
A
of
IC26
provides
buffering
action
between
the
oscillator
and
the
first
decade
divider
(1C25)
of
the
time
base
scaler.
The
10
MHz
clock
signal
is
then
further
divided
by
IC’s
19
through
24
to
provide
appropriate
GATE
times
for
the
frequency
mode
and
time
pulses
for
the
period
mode.
GATING,
MEMORY,
RESET
Frequency
Mode
The
input
signal
at
1C2B
pin
4
is
coupled
through
gates
B
and
E
of
IC2
to
the
counters
(IC3
through
IC7)
by
the
GATE
pulse
(one
second
or
one
millisecond)
from
pin
11
of
1C13B.
During
this
count
time,
O05
and
D106
(the
GATE
lamp)
are
turned
on.
At
the
end
of
the
GATE
pulse,
pin
10
of
1C13B
goes
high.
This
causes
pin
11
of
IC18D
to
pulse
low,
and
pin
8
of
IC18C
to
pulse
high
and
turn
on
Q6
for
an
instant.
During
this
instant,
IC’s
8
through
12
accept
the
count
from
the
five
decade
counters
and
begin
to
display.
The
frequency
is
displayed
until
the
end
of
the
next
GATE
pulse
when
the
display
is
updated.
4
If
the
display
was
in
overrange,
1C13A
pin
15
would
be
high
and
this
overrange
condition
would
be
entered
in
data
latch
>
1C14.
The
high
at
the
output
of
1C14
would
allow
the
~
overrange
indicator
to
light.
Under
conditions,
1C14
keeps
the
indicator
off.
non-overrange