July 2013 9.1 PLC Functions 1665
Detection of pulses
at PLC-inputs
The following data apply for single-channel standard PLC inputs and dual-
channel FS inputs of the safe PLC (SPLC).
Minimum required pulse widths in the HSCI system for signal detection by the
control at the standard inputs:
The (S)PLC cycle time must also be observed for actual processing in the
(S)PLC program. The pulse width must be longer than the above mentioned
time + the (S)PLC cycle time in order to ensure that the pulse is processed in
the (S)PLC program.
Minimum required pulse widths in the HSCI system for signal detection by the
control at the special inputs:
Pulse widths at (S)PLC inputs that are not detected due to internal hardware
filter run times:
Some devices that operate with self-generated test pulses at their input (e.g.
test pulses for wire breakage or cross-circuit detection) should be connected
to machines at the (S)PLC inputs. For example, a low test pulse (high --> low
flank) of such devices must be smaller than 2.0 ms so that they are not
detected due to internal filter run times. If pulses are greater than 2.0 ms it can
cause the control to detect them, forward them to the (S)PLC run-time
environment and trigger the corresponding reactions.
Input Required pulse
width
(S)PLC inputs on: X9 of a PLB, PLD in slots 1 to 4,
machine operating panel or UxC 1xx
> 8 ms
PLC inputs on PLD in slots 5 to 8 > 11 ms
Input Required pulse
width
Fast PLC inputs on PLD in slots 1 to 4 > 8 ms
Emergency stop inputs –ES.A, –ES.B > 5.5 ms
Input Maximum
pulse
width
Effect
All (S)PLC inputs
Edge low --> high
< 0.4 ms High pulse is not
detected due to
internal filter run times
All (S)PLC inputs
Edge high --> low
< 2.0 ms Low pulse is not
detected due to
internal filter run times
To Next Page
Loading...
