Hitachi SH7032 - Page 11

Section Page Description Edition
2.1.2 Control
Registers
Figure 2.2 Control
Registers
18 Description amended
Bits I3–I0: Interrupt mask bits.
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2.1.4 Initial Values
of Registers
Table 2.1 Initial
Values of Registers
19 Description amended
SR Bits I3–I0 are 1111(H'F), reserved bits are 0, and other
bits are undefined
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3.1 Types of
Operating Modes and
Their Selection
Table 3.1 Operating
Mode Selection
49 Note amended
*2 Only modes 0 and 1 are available in the SH7032 and SH7034
ROMless version.
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8.11.3 Maximum
Number of States
from BREQ Input to
Bus Release
Figure 8.47 Bus
Release Procedure
174 Description amended
t
BACD2
t
BRQS
t
BACD1
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9.1.4 Register
Configuration
Table 9.2 DMAC
Registers
179 *4 added
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9
are ignored. For details on the register addresses, see section
8.3.5, Area Descriptions.
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9.3.4 DMA Transfer
Types
200 Description amended
Line 3
⋅⋅⋅ destination or source must be the SCI or A/D converter
(table 9.4). ⋅⋅⋅
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10.1.4 Register
Configuration
Table 10.3 Register
Configuration
230 *2 description amended
*2 Only 0 can be written to clear flags.
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10.4.5 Reset-
Synchronized PWM
Mode
Procedure for
Selecting Reset-
Synchronized PWM
Mode (figure 10.31):
268 Description amended
4. Set bits CMD1 and CMD0 in TFCR to select reset-synchronized
PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and
TOCXB4 become PWM output pins.
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