Section Page Description Edition
10.4.6
Complementary
PWM Mode
Procedure for
Selecting
Complementary
PWM Mode (Figure
10.33):
271 Description amended
3. Set bits CMD1 and CMD0 in TMDB to select complementary PWM
mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and
TOCXB4 become PWM pins.
6
10.6.15 ITU
Operating Modes
Table 10.18 ITU
Operating Modes
(Channel 0)
301 Table amended
Register Setting
TSNC TMDR TFCR TOCR TIOR0 TCR0
Operating
Mode Sync MDF FDIR PWM
Comp
PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB
Clear
Select
Clock
Select
Synch-
ronized
preset
SYNC0
= 1
——√ ——— — √√ √√
PWM √ — — PWM0
= 1
——— — — √ * √√
Output
compare A
function
√ — — PWM0
= 0
— — — — IOA2 = 0,
others:
don’t care
√√√
6
Table 10.19 ITU
Operating Modes
(Channel 1)
302 Table amended
Register Setting
TSNC TMDR TFCR TOCR TIOR1 TCR1
Operating
Mode Sync MDF FDIR PWM
Comp
PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB
Clear
Select
Clock
Select
Synch-
ronized
preset
SYNC1
= 1
——√ ——— — √√ √√
PWM √ — — PWM1
= 1
——— — — √
*
√√
Output
compare A
function
√ — — PWM1
= 0
— — — — IOA2 = 0,
others:
don’t care
√√√
6
Table 10.20 ITU
Operating Modes
(Channel 2)
303 Table amended
Register Setting
TSNC TMDR TFCR TOCR TIOR2 TCR2
Operating
Mode Sync MDF FDIR PWM
Comp
PWM
Reset
Sync
PWM Buffer
Output
Level
Select IOA IOB
Clear
Select
Clock
Select
Synch-
ronized
preset
SYNC2
= 1
——√ ——— — √√ √√
PWM √ — — PWM2
= 1
——— — — √
*
√√
Output
compare A
function
√ — — PWM2
= 0
— — — — IOA2 = 0,
others:
don’t care
√√√
6
12.1.4 Register
Configuration
Table 12.2 WDT
Registers
337 *4 added
Initial
Address
*
4
Name Abbreviation R/W Value Write
*
1
Read
*
2
Timer control/status register TCSR R/(W)
*
3
H'18 H'5FFFFB8 H'5FFFFB8
Timer counter TCNT R/W H'00 H'5FFFFB9
Reset control/status register RSTCSR R/(W)
*
3
H'1F H'5FFFFBA H'5FFFFBB
Notes: *1 Write by word transfer. A byte or longword write cannot be used.
*2 Read by byte transfer. The correct value cannot be obtained by a word or longword
read.
*3 Only 0 can be written in bit 7, to clear the flag.
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions
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