Hitachi SH7032 - Page 172

137
T1
CK
A21–A0
CSn
RD
AD15–AD0
T2
WRH, WRL
AD15–AD0
Read
Write
When
RDDTY
= 0
When
RDDTY = 1
Figure 8.12 Basic Timing of External Memory Space Access (2-State Read Timing)
High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit
(RDDTY) in BCR. When RDDTY is set to 1, the high-level duty is 35% of the T1 state, enabling
longer access times for external devices. Only set to 1 when the operating frequency is a minimum
of 10 MHz.