174
(c) Refresh cycle + bus cycle
The bus is never released during a refresh cycle and the following bus cycle ((a) or (b)
above)) (figure 8.46).
Refresh cycle
Cycle during which bus
is not released
1 bus cycle
Figure 8.46 Refresh Cycle and Following Bus Cycle
2. Bus release procedure
The bus release procedure is shown in figure 8.47. Figure 8.47 shows the case where BREQ is
input one state before the break between bus cycles so that tBRQS is satisfied. In the SH7032
and SH7034, the bus is released after the bus cycle in which BREQ is input (if BREQ is input
between bus cycles, after the bus cycle starting next).
CK
A21 to A0
BREQ
BACK
RD, WR
RAS, CAS
CSn
t
BRQS
t
BRQS
t
BZD
t
BZD
t
BACD2
t
BACD1
Bus cycle Bus cycleBus release
Strobe pin:
high-level output
The bus is released after the bus
cycle in which BREQ is input
(if BREQ is input between bus cycles,
after the bus cycle starting next).
Bus cycle restart
Address & data
strobe pins:
high impedance
Figure 8.47 Bus Release Procedure
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