207
CK
DREQ
DACK
Bus cycle
CPU CPU CPU
DMAC (R) DMAC (W)
CPU CPU CPU
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: Illustrates the case when DACK is output during the DMAC write cycle.
Figure 9.16 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States)
CK
DREQ
DACK
Bus cycle
T2TwT1
DMAC
T2TwT1
CPUCPUCPU DMACCPU CPU
Note: When DREQ is negated at the third state of the DMAC cycle, the next DMA transfer will
be executed because the sampling is performed at the second state of the DMAC cycle.
Figure 9.17 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 2 States + 1 Wait
State)
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